JPH04160378A - Integrated circuit and method of observing signal of the same - Google Patents

Abstract

PURPOSE:To perform an efficient observation by providing an integrated circuit, a shift register and a memory element and observing the output of the memory element by an observing device. CONSTITUTION:Clock pulses outputted from a clock source 8 are inputted to an integrated circuit 1 and a shift register 10, a control pulse generated by dividing the frequency of the clock pulse by (n) is inputted to the integrated circuit 1 and a memory circuit 11. The integrated circuit 1 fixes the conditions of (n) inside positions wherein the signal is observed every time when the circuit 1 receives the control pulse and outputs a signal indicative of the condition as a serial signal of (n) bits according to the clock pulse. The shift register 10 receives the serial signal in synchronism with it. Then, when the next control pulse is received, the memory circuit 11 reads the state of the shift resistor 10 and fixes the state until the subsequent control pulse is received. By observing a parallel signal of (n) bits outputted from the memory circuit 11 by an observing instrument such as a logic analyzer, the state of a logic circuit 2 in the integrated circuit 1 becomes clear.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated circuit and a signal observation method for the integrated circuit, and particularly to an integrated circuit that outputs observation information from the integrated circuit through a single output line, and a method for observing signals from the integrated circuit. Concerning signal observation methods.

[Conventional technology]

The conventional method for observing integrated circuits and their signals involves attaching logic analyzer probes to all of the terminals to be measured on the integrated circuit. For this reason, good connections were made to all the terminals to be measured, either directly or via a lead wire of several centimeters, or by preparing sockets for integrated circuits or special probes. .

[Problem to be solved by the invention]

The conventional integrated circuits and integrated circuit signal observation methods described above are as follows:
For each integrated circuit that requires observation, ensure a good connection to all the terminals under test, either directly or via a lead wire of several cm, or by preparing a socket for integrated circuits or a special probe. Therefore, if there are many terminals to be measured, there is a problem that attention and a lot of effort are required.

An object of the present invention is to provide an integrated circuit that can easily ensure a good connection state, save labor, and perform efficient observation even if there are many terminals to be measured or a large number of integrated circuits to be measured. and to provide a signal observation method for integrated circuits.

[Means to solve the problem]

The integrated circuit of the present invention includes a memory element that is connected to a plurality of points in a logic circuit main body where signals are to be observed and that stores a state in response to an external control pulse, and a memory element that receives the output of the memory element and performs parallel-to-serial conversion. The configuration includes a shift register that receives clock pulses from the outside and outputs them as serial signals.

The signal observation method of an integrated circuit according to the present invention detects the state of a plurality of internal signal observation points by receiving a control pulse from the outside.
an integrated circuit that has a function of storing the parallel signal as a parallel signal and then outputting the parallel signal as a serial signal to one output line according to an external clock pulse; a shift register that increments according to the frequency and outputs it as a serial-to-parallel converted serial signal; a frequency divider that divides the clock pulse by a number equal to the number of the signal observation target points and outputs it as the control pulse; A storage element is provided for accumulating parallel signals output from the shift register, and the output of the storage element is sent to an observation device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an integrated circuit according to an embodiment of the present invention.

The integrated circuit 1 includes a logic circuit 2, a memory circuit 3 for storing the states of a plurality of signal observation target locations in the logic circuit 2, and the memory contents of the memory circuit 3 as Nll parallel signals and parallel signals. It consists of a shift register 4 that converts serial signals and outputs them as serial signals, and receives clock pulses on a clock signal line 5 and control pulses on a control signal line 6 as control signals from the outside, and outputs them as an observation signal output line. 7. At this time, logic circuit 2
If the number of signal observation target points is n, the memory circuit 3 is provided with a function of simultaneously storing n-bit parallel signals, and the n signal observation target points and the memory circuit 3
It is connected to each storage section through n signal lines.

Next, the operation will be explained.

When the logic circuit 2 receives a control pulse from the outside on the control pulse signal line 6 during operation, the storage circuit 3 simultaneously stores the state of the signal observation target portion of the logic circuit 2 as an n-bi-soto parallel signal. The n-bit parallel signal stored in the storage circuit 3 is immediately input to the shift register 4.

When the shift register 4 receives a clock pulse on the clock signal line 5, it converts the already received n-bit parallel signal from parallel to serial and outputs it to the observation signal output line 7 as a serial signal. After outputting the n-bit serial signal, a control pulse arrives again on the control pulse signal line 6, and the storage circuit 3 simultaneously stores the state of the signal observation target part of the logic circuit 2 as an n-bit parallel signal. Repeat the same operation as above.

FIG. 2 is an explanatory diagram for explaining one embodiment of the integrated circuit signal observation method of the present invention.

The integrated circuit 1 receives clock pulses transmitted from a clock source 8 via a clock signal line 5, and further receives clock pulses sent from a clock source 8 via a frequency divider 9.
receives the control pulse generated by dividing the clock pulse by n via the control pulse signal line 6. -The integrated circuit 1 is
It receives the clock pulse and the control pulse, and outputs the state of the signal observation target location to the observation signal output line 7 as an n-bit serial signal. A shift register 10 is connected to the observation signal output line 7. The shift register 10 receives the clock signal sent from the clock source 8, reads an n-bit serial signal bit by bit, and outputs it as an n-bit parallel signal. The n-bi-soto parallel signal output from the shift register 10 is sent to the storage circuit 11.
It is output to . When the storage circuit 11 receives the control 7N67 response output from the frequency divider 9, it reads and stores the n-bi-soto parallel signal output from the shift register 10. The output of this memory circuit 11 is input to observation equipment such as a logic analyzer.

Next, the operation will be explained.

The clock pulse output from the clock source 8 is transmitted to the integrated circuit 1.
is input to the shift register 10, and the control 7N6 pulse generated by dividing this clock pulse by n is applied to the integrated circuit 1.
and is input to the memory circuit 11. Every time the integrated circuit 1 receives a control pulse, it fixes the states of n internal signal observation target locations and outputs it as an n-bit serial signal in accordance with the clock pulse. The shift register 10 receives this serial signal in synchronization. When the next control pulse is received, the storage circuit 11 reads the state of the shift register 10 and fixes it until the next control pulse is received. By observing the n-bit parallel signal output from the memory circuit 11 with an observation device such as a logic analyzer, the state of the logic circuit in the integrated circuit 1 becomes clear. At this time, only three signal lines are connected between the integrated circuit 1 and the observation circuit. Therefore,
The connection between the integrated circuit 1 and the observation circuit is easy, and if you connect the observation circuit and the logic analyzer in advance, you can easily change the connection even when observing multiple integrated circuits 1. It is very convenient because it can be done.

Furthermore, by using a frequency divider with a variable frequency division number, even if there are multiple types of integrated circuits and the number of observation points for each is different, the measurement equipment can be configured with the same configuration. becomes.

〔Effect of the invention〕

As explained above, the present invention stores the states of a plurality of internal signal observation target locations as parallel signals in response to external control pulses, and then converts the parallel signals into serial signals in accordance with external clock pulses. An integrated circuit that has the function of outputting to one output line, and a shift register that receives the serial signal output from this integrated circuit, steps it according to an external clock pulse, converts it from serial to parallel, and outputs it as a parallel signal. A frequency divider divides the clock pulse by a number equal to the number of points to be observed and outputs it as the aforementioned control pulse, and a storage element stores the parallel signal output from the shift register according to the control pulse. By observing the output of the memory element with an observation device, even if there are many terminals to be measured or a large number of integrated circuits, it is possible to easily ensure a good connection state, save labor, and perform efficient observation. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an integrated circuit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram for explaining an embodiment of a signal observation method for an integrated circuit according to the present invention. 1...Integrated circuit, 2...Logic circuit, 3
, 11... Memory circuit, 4.10... Shift register, 5... Clock signal line, 6...
...Control pulse signal line, 7...Observation signal output line, 8...Clock source, 9.Old...Frequency divider. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Scope of Claims] 1. A memory element connected to a plurality of points of the logic circuit main body where signals are to be observed and receives a control pulse from the outside to store the state, and a memory element that receives the output of the memory element and performs parallel-to-serial conversion. and a shift register that receives a clock pulse from an external source and outputs it as a serial signal. 2. A function that receives control pulses from the outside to store the status of multiple internal signal observation points as parallel signals, and then outputs this parallel signal to a single output line as a serial signal according to clock pulses from the outside. a shift register that receives the serial signal output from the integrated circuit, increments it in accordance with the clock pulse, performs serial-to-parallel conversion, and outputs it as a parallel signal; a frequency divider that divides the frequency by a number equal to and outputs it as the control pulse, and a storage element that stores the parallel signal output from the shift register according to the control pulse,
A signal observation method for an integrated circuit, characterized in that the output of the memory element is sent to an observation device.