JPH04157733A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable increase in parasitic capacity to be controlled and gate length and gate resistance to be reduced by forming a resist pattern for upper electrode, etching a dummy gate, and forming a T-type gate within a gate recess by deposition and shift-off of a gate metal. CONSTITUTION:A spacer layer 6 is eliminated by etching with a resist pattern 7 as a mask. A deposition metal for forming a dummy gate 8 is deposited. An unneeded metal 8 is eliminated by lift-off. A GaAs activation layer 2 is etched from a gap between the spacer layer 6 and the deposition metal for forming a dummy gate 8, thus forming a gate recess 9. The spacer layer 6 and the deposition metal for forming a dummy gate 8 are eliminated by etching. A resist 10 is applied on an entire surface of the wafer and the gate recess 9 is buried again. The resist 10 is made thin by dry etching, thus enabling it to remain within the gate recess 9 only. A resist pattern for forming gate electrode 11 is formed. The dummy gate is eliminated by etching. A metal for gate electrode 5A is deposited with a resist pattern 10A remaining within the recess as a mask. Finally, a T-type gate electrode 5 is obtained and an FET structure is formed.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to a method for manufacturing a semiconductor device.
The present invention relates to a method for forming gate electrodes of field effect transistors (hereinafter referred to as FΣT), high electron mobility transistors (hereinafter referred to as HEMT), and the like.

[Conventional technology]

Generally speaking, in order to improve the performance of high-frequency FETs, the gate length (Lg
), a reduction in gate resistance (lLg) is required.

For this reason, the lower part of the gate electrode is narrower and the upper part is wider. A T-shaped gate structure is used.

In addition, due to the requirement for high voltage resistance, a structure that also includes a gate recess structure is used, making its manufacture a national problem.

FIGS. 2(a) to 2(f) are cross-sectional views showing the process of forming a T gate electrode in the groove of a conventional FET. In the figure, (1) is the substrate, (2) is the active layer, (
3) is a source electrode, (4) is a drain electrode, and (5) is a gate electrode.

(6), (6) is a SiN or SiON spacer layer,
(6A).

(12A) is the remainder of the SiN or SiON spacer layer;
-(7).

01 is a resist.

Next, the conventional manufacturing process will be explained. A source electrode (
4) and a drain electrode (5) are formed, and a spacer layer (6) of SiN or SiON is formed on the entire surface. Then, using the resist pattern (7) for gate recess formation as a mask, the spacer layer (6) is removed by etching. Etch to form gate recess (9) (No. 21!1 (b)) o Further resist (7)
) after removing JN so that the gate recess (9) is filled.
Or form a SiON spacer layer (8112)
Figure (c)) o Then, when the thickness of the spacer layer @ is removed by dry etching, the remainder (12A) of the spacer layer (2) remains at both corners of the gate recess (9) at one step (second
Figure (d)).

Next, a resist pattern 0 for forming a gate electrode is formed, and a metal for the gate electrode (5A) is formed by vapor deposition (FIG. 2(e)). Unwanted metal (
5A) and the resist (2) are removed and dry etching is performed to obtain a T-shaped gate electrode (5) to form an FET structure (FIG. 2(f)).

[Problem to be solved by the invention]

To form a T-shaped gate with a conventional gate recess structure, the manufacturing process shown in Figure 2 was used, so after the T-shaped gate was formed, the remaining spacer layer (12A) remained in the gate recess, and the gate S between the electrode and the G&Aa active layer
There is a problem in that the parasitic capacitance due to the dielectric film such as iN or SiON increases, impairing the high frequency characteristics of FET etc. and reducing the effect of shortening the gate length. This invention is aimed at solving the above problems. An object of the present invention is to obtain a method of manufacturing a semiconductor device that can shorten the gate length and reduce the gate resistance.

[Gamma method to solve problems]

The method for manufacturing a semiconductor device according to the present invention suppresses an increase in parasitic capacitance using a T-shaped gate with a recessed structure, and provides a method for manufacturing a semiconductor device that can shorten the gate length and reduce gate resistance. Then, form a gate recess, backfill the inside of the gate recess with resist, and etch back the resist until the top of the dummy gate is exposed.
After forming the resist pattern for the upper electrode, the dummy gate is etched, and gate metal is deposited and lifted off.
A T-shaped gate is formed within the gate recess.

[Effect]

The method of manufacturing a semiconductor device according to the present invention suppresses an increase in parasitic capacitance in a T-shaped gate having a recessed structure, shortens the gate length and reduces gate resistance, and obtains a field effect transistor with high breakdown voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figure (ml-1) is a cross-sectional view showing the manufacturing process of a semiconductor device which is an embodiment of the present invention.
(2) is the active layer, (3) is the source electrode, (4) is the drain electrode, (5) is the gate electrode, (6) is SiN or S
iON spacer layer i7), σ0.01 is resist (8
) is the vapor-deposited metal for forming a dummy gate, and (9) is the gate recess.

Next, two manufacturing processes will be explained. First, a semiconductor substrate (
1) Source electrode (4) on the active layer (2) grown on it
A drain electrode (5) is formed, and the entire surface of the wafer is covered with Si.
A spacer layer (6) of N or 5 ION is formed (FIG. 1 fa)). After that, a resist pattern (7) for processing the spacer layer (6) is formed (FIG. 1(b)).
The spacer layer (6) is removed by etching using the resist pattern (71) as a mask (FIG. 1(c)). Then, the vapor-deposited metal (8) for forming a dummy gate is deposited (FIG. 1(c)).
d)) Lift-off removal of unnecessary metal (7A) at 0th order (
Figure 1(e)).

Then, the caAs active layer (2) is etched from the gap between the spacer layer (6) and the dummy gate-forming vapor-deposited metal (8) to form a gate recess (9) (Fig. 1))
.

Further, the spacer layer (6) and the deposited metal (8) for forming a dummy gate are removed by etching (FIG. 1(g)). Next, a resist (11) is applied to the entire surface of the wafer, and a gate recess (9) is applied.
) (Figure 1 (h)). Next, Regis) (
11) is thinned by dry etching and left only in the gate recess (9) (FIG. 1(t)). Next, form a resist pattern 0υ for gate electrode formation (l!1
(Fig. 1 (j)) Next, the dummy gate is removed by etching (Fig. 1 (k)) o 'f: Then, using the resist pattern (IOA) remaining in the recess as a mask, the gate electrode metal (5A ) Figure 1 (1)) Finally, remove unnecessary metal (5A) and resist (10A) by lift-off method, and form T-shaped gate electrode (
5) to form an FKTll structure (Fig. 5-).

〔Effect of the invention〕

As described above, according to Kouni's invention, a dummy gate and a gate recess are formed, the inside of the gate recess is backfilled with resist, the resist is etched back until the top of the dummy gate is exposed, and after the resist pattern for the upper electrode is formed, the dummy gate is etched back. Etching the gate and depositing gate metal
Since a T-shaped gate is formed within the gate recess by lift-off, the dielectric film is not exclusively located directly under the gate electrode.

A T-shaped gate with a recessed structure suppresses an increase in parasitic capacitance, and can shorten the gate length and reduce gate resistance with high breakdown voltage, which has the effect of making it possible to obtain a high-performance FET in a high frequency range.

[Brief explanation of drawings]

FIG. 1(a)-1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (f) are cross-sectional views showing the manufacturing process of a conventional semiconductor device. be. In the figure, C1) is the substrate, (2) is the active layer, (3) is the source electrode, (4) is the drain electrode, (5) is the gate electrode, (6) is the SiN or SiON spacer layer, (7) is the
, α1.01 is the resist), (8) is the evaporated metal for dummy gate formation, 9) is the gate recess, (6A),
(12A) shows the remainder of the SiN or SiON spacer layer. In Figure 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] After forming source/drain electrodes on one main surface of the semiconductor substrate, forming a SiN or SiON spacer layer on the entire surface of the wafer, forming a resist pattern for forming a dummy gate electrode, and vapor depositing metal for forming a dummy gate electrode. a step of etching the substrate using the spacer layer and the deposited metal as a mask after removing the resist pattern; a step of etching and removing the spacer layer and the deposited metal; a step of applying a resist to the entire surface of the wafer and etching the resist to remove the etched metal; forming a resist pattern for an upper gate electrode wider than the dummy gate electrode on the top of the dummy gate electrode; A method for manufacturing a semiconductor device, comprising the steps of removing by etching, depositing metal for a gate electrode, and lifting off unnecessary metal to complete a gate electrode to form a field effect transistor.