JPH04156630A - Memory controller - Google Patents

Abstract

PURPOSE:To shorten the time required for the initialization of a memory by outputting a control signal controlling a corresponding unit when addresses set in respective unit storage areas or a specified address are inputted. CONSTITUTION:A memory controller 11 controls the write/read of data as against the memory 13 based on an address signal ADDR given from CPU 12, data DATA and the control signal SS. The memory 13 is divided into memory banks M1-M4 having the same storage capacity of A-byte. The controller 11 includes decoding circuits DMI-DM4 corresponding to the banks M1-M4. When the addresses which are set in the corresponding memory bank is given based on the signal ADDR, the circuits DM1-DM4 output the control signals MEM1-MEM4 controlling the memory bank. In the case of write control, a write instruction, the address and data to be written are included in the signals, and a read instruction and the address are included in the case of reading.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory control device suitably implemented in a processing device such as a workstation equipped with a large capacity memory of, for example, several tens of megabytes.

BACKGROUND ART FIG. 4 is a block diagram showing a configuration related to a conventional memory control device 1. The memory control device 1 includes a CPU (
Address signal ad given from central processing unit) 2
The memory 3 is controlled based on dr, data, and control signal SS. The memory 3 is composed of four memory banks m1 to m4, each having the same storage capacity. If the storage capacity of one memory bank is A bytes, then the storage capacity of memory 3 is A x 4
Becomes a part-time worker. The memory control device 1 controls data writing and reading on a memory bank basis.

FIG. 5 is a diagram showing an address map of the memory 3 set in the CPU 2 by the memory control device 1.

Address 0 to address A-1 are set in memory bank m1, address 0 to address 2-1 are set in memory bank m2, and address 2A to address 3-1 are set in memory bank m3. is set,
Memory bank m4 has addresses 3A to 4A-1.
is set.

Therefore, from CPU2 to address O to address A-1
When the space is accessed, the memory control device 1 outputs a control signal meml that controls the memory bank m1. This control signal meml causes data to be read/written to a specified address within the memory bank m1.

Similarly, when the space from address A to address 2A-1 is accessed, control signal mem2 that controls memory bank m2 is output, and access 2A to access 3A-1 is accessed.
When the space at address 3A to address 4A-1 is accessed, a control signal mem3 for controlling memory bank m3 is output, and when the space from address 3A to address 4A-1 is accessed, control signal mem4 for controlling memory bank m4 is output. In this way, the number of memory banks controlled by a given address signal addr is one.

Problems to be Solved by the Invention FIG. 6 is a timing chart for explaining the initialization (zero clearing of the memory 3) operation that is performed in the memory control device 1 shown in FIG. 4, for example, when the power is turned on. . Initialization of the memory 3 is performed by sequentially specifying each address O to address 4A-1 of the memory 3 and writing data "0" to the storage area corresponding to the specified address. Therefore, as shown in FIG. 6(1), in the period tal, addresses O~
By sequentially specifying addresses A-1,
4), the memory control device 1 sends a control signal m.
e m 1 is output. Similarly, in the period ta2, by giving addresses A to 2A-1, the memory control device 1 sends the control signal m as shown in FIG. 6(5).
em2 is output.

Period ta3. In ta4, Figure 6 (6) and Figure 6 (
As shown in 7), the control signals mem3. mem
4 is output. Therefore, the time ta required to initialize the memory 3 is ta=tal+ta2+ta3
+ta4...(1).

Here, during the period tal to ta4, tal=ta2
=ta3=ta4... Since the relationship (2) exists, the period ta is ta=4・tal...
(3) becomes. Therefore, the number of memory banks is n(n
In the case of ≧1), the period ta is ta=n・tal...
(4) becomes.

As described above, there is a problem that the larger the memory capacity, the longer the period ta required for initializing the memory.

An object of the present invention is to provide a memory control device that can shorten the time required to initialize a memory.

Means for Solving the Problems The present invention sets a different address for each unit storage area in a memory having a predetermined number of unit storage areas, and divides the memory into a plurality of units each having an equal number of unit storage areas. In a memory control device that controls the memory by dividing it into multiple units, an address provided corresponding to each of the plurality of units and set in each unit storage area of the corresponding unit, or an address set in each unit storage area of the memory is The memory control device is characterized in that it includes a plurality of unit control means that outputs control signals for controlling corresponding units when different predetermined specific addresses are input.

According to the present invention, when an address set in each unit storage area is given, the unit control means corresponding to the unit including the unit storage area to which the address is set outputs a control signal to the unit.

The control signal includes a write command, address, data to be written, etc. in the case of data write control, and includes a read command, address, etc. in the case of data read control.

Moreover, when a predetermined specific address is given, the plurality of unit control means each output a control signal to control the corresponding unit. This makes it possible to control a plurality of units simultaneously, and for example, it is possible to shorten the time required for so-called memory initialization processing in which data rQ is written to all unit storage areas.

Embodiment FIG. 1 shows a memory control device 11 which is an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration related to the above.

The memory control device 11 controls the memory 1 based on an address signal ADDR given from the CPU 12, data DATA, and a control signal SS representing a write command or a read command.
Controls writing/reading of data to/from 3. The memory 13 includes memory banks M1 to M, which are units each having the same storage capacity, here A byte of storage capacity.
It is divided into 4 parts.

The memory control device 11 is configured to include decoding circuits DMI to DM4, which are unit control means corresponding to the memory banks M1 to M4, respectively. Each decoding circuit D
When MI-DM4 receives an address set in a corresponding memory bank based on address signal ADDR given from CPUI2, it outputs control signals MEM1-MEM4 for controlling the corresponding memory bank. These control signals MEM1 to MEM4 each include a write command, address, data to be written, etc. in the case of write control, and include a read command, address, etc. in the case of read control.

FIG. 2 is a diagram showing an address map of the memory 13 set in the CPU 12 by the memory control device 11. As shown in FIG. 2, address 0 to address A-1 are set in memory bank M1, address 0 to address 2A-1 are set in memory bank M2, and address 0 to address 2A-1 is set in memory bank M3. 2A~Address 3
A-1 is set, and addresses 3A to 4A-1 are set in memory bank M4. Also CP
Addresses B to B+A-1 are set in U12 for designation when simultaneously accessing memory banks M1 to M4.

Here, the operation of the decoding circuit DMI will be explained.

The decoding circuit DMI outputs the control signal MEM1 to the memory bank M1 when the condition shown in Equation 5 below is satisfied. Therefore, address 0 to address A-1 or address B to address B+A-1 is address signal A.
Control signal MEM1 is output when specified by DDR.

Similarly, the decoding circuits DM2 to DM4 receive the control signal M when the conditions of the following formulas 6 to 8 are satisfied, respectively.
EM2 to MEM4 are output to memory banks M6 to M8, respectively.

Control signal MEM1 is valid = Address is 0 or more and A-1 or less OR address is B or more and B+A-1 or less...(5) Control signal MEM2 is valid = Address is A or more and 2A-1 or less OR address is B or more and B+A- 1 or less...(6) Control signal MEM3 is valid = address is 2A or more 3A-1
Below OR address is B or more and B+A-1 or less... (7) Control signal MEM4 is valid = address is 3A or more and 4A-1
Below, the OR address is greater than or equal to B and less than or equal to B+A-1... (8) However, since address B to address B+A-1 are virtually set addresses, the address B is ~ Only when address B+A-1 is specified, the control signal MEM
1 to MEM4 are output respectively.

FIG. 3 is a timing chart for explaining the initializing operation of the memory 13. From CPU12,
As shown in FIG. 3 (1), the address signal ADDR counts up by 1 from address B, and increases to address B+.
The data DATA is sequentially output up to A-1, and in synchronization with the address signal ADDR, data "0" is output as shown in FIG. 3(2). Also at this time, CPU12
As shown in FIG. 3 (3), a control signal SS as a write command is outputted from the .

The decode circuits DMI to DM4 are supplied with a control signal SS as a write command as well as address B to address B+A-1.
are given, so the control signals MEMI-MEM4 are outputted to control the memory banks M1-M4, respectively, as described above. Therefore, when address B is input, the storage area corresponding to address "0" of memory bank M1, the storage area corresponding to address "A" of memory bank M2, and the address "2A" of memory bank M3 are Corresponding storage area and address “3A” of memory bank M4
Data "0" is written to the storage areas corresponding to the respective storage areas. In this manner, as the input address increases from address B, data "0" is sequentially written from the storage area corresponding to the lower address of each memory bank to the storage area corresponding to the upper address. As a result, the period Ta
Initialization of the memory 13 is completed.

Here, the memory space from address B to address B+A-1 is A byte, which is the same as each memory space of memory banks M1 to M4. Therefore, the time required to access all the storage areas of one memory bank is the same as when using the conventional memory control device N1. Therefore, the period Ta is Ta=tal
−(9>, therefore Ta=ta/4 − (10
). In other words, for example, the time required to initialize a memory with a memory capacity of AX4 bytes is reduced to 1/1 compared to the conventional method.
It can be shortened to 4. This allows you to initialize the memory in a short time, making it possible to initialize the memory in a short time. 11 and memory 13, startup processing such as when power is turned on can be performed at high speed.

In addition, although this embodiment has been described assuming that the memory capacity is AX4 bytes, it is also possible to increase the number of memory banks and, for example, increase the memory capacity to A×N bytes (N=5.6
．． ), the time required to initialize the memory is the period Ta.

As described above, according to this embodiment, it is possible to control data writing to a plurality of memory banks simultaneously, and the time required for initializing the memory 13 can be significantly shortened.

As a result, in a processing device such as a computer or a workstation equipped with the memory control device 1 according to the present invention, it is possible to perform startup processing (memory initialization) of the processing device at high speed, for example, when the power is turned on.

Effects of the Invention As described above, according to the present invention, a plurality of units constituting a memory can be controlled simultaneously, and the time required for so-called memory initialization can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration related to a memory control device 11 which is an embodiment of the present invention, FIG. 2 is a diagram showing an address map set in the CPU 12, and FIG. 3 is an initial diagram of the memory 13. FIG. 4 is a block diagram showing the configuration related to the conventional memory control device 1, FIG. 5 is a diagram showing the address map set in the CPU 2, and FIG. 5 is a timing chart for explaining the initialization operation of the memory 3. FIG. 11...Memory control device, 12...cPU, 13.
・・Memory, DMI to DM4 ・・Decode circuit, M1
~M4...Memory bank, MEMI~MEM4...
Control signal agent Patent attorney Number of strokes Keiichi 3rd figure

Claims (1)

[Claims] Control is performed by setting a different address for each unit storage area in a memory having a predetermined number of unit storage areas, and dividing the memory into a plurality of units each having an equal number of unit storage areas. In a memory control device, an address provided corresponding to each of the plurality of units and a predetermined address different from an address set for each unit storage area of the corresponding unit or an address set for each unit storage area of the memory. A memory control device comprising a plurality of unit control means that outputs control signals for controlling corresponding units when an address is input.