JPH0447348A - Memory control circuit - Google Patents

Abstract

PURPOSE:To read and write optional continuous data by outputting an address strobe signal, a write-in instructing signal, and a data output instructing signal, etc., in the number of necessary cycles, and utilizing the page access system of a dynamic RAM. CONSTITUTION:A data buffer 12 controls the input/output of the data at the time of reading and writing the data between a CPU 1 and a main storage circuit 5. The CPU 1 outputs a command to write an address to an address bus and write the optional number of the data to a command bus, and simultaneously, it makes main storage access continuation signal 8 active. A main storage access control circuit 9 outputs the address strobe signal and the write-in instructing signal to the main storage circuit 5, and further, it outputs an address summing signal 10 to an address addition circuit 7. Thus, write-in data is written in the continuous addresses. Thus, the optional continuous data can be read and written.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit, and particularly to a memory control circuit that controls continuous reading of data from a main memory circuit and continuous writing of data to the main memory circuit.

[Conventional technology]

Conventionally, this type of main memory circuit has been increased in capacity by using an inexpensive refresh memory (for example, dynamic RAM) as a storage element, and has also been developed using a dynamic RA that can be accessed at high speed.
Although speeds are being increased using M, the speed of the main memory circuit is much slower than that of the central processing unit (hereinafter referred to as CPU).

Therefore, when reading or writing data with consecutive addresses, a page access method, which is generally known as a function of dynamic RAM, is used to divide the main memory into blocks of a certain size. A function that allows units to be read in one main memory access (
Main memory accesses by the CPU are sped up by a function (hereinafter referred to as "block write") that allows data to be written in blocks by a single access to the main memory (hereinafter referred to as "block read").

[Problem to be solved by the invention]

In the conventional main memory circuit access method described above, when reading or writing data with consecutive addresses,
Although the speed is increased by the block read or block write function, if the continuous data is larger than a block unit, the block read or block write must be performed multiple times. Another disadvantage is that if the continuous data is smaller than a block unit, extra time is required.

[Means to solve the problem]

The memory control circuit of the present invention is provided between a central processing unit and a main memory circuit, and includes an address addition circuit that sequentially adds main memory access addresses from the central processing unit, and an address addition circuit that sequentially adds main memory access addresses from the central processing unit; It has means for sequentially reading data from a main memory access address and means for writing data in response to a main memory command for accessing a number and a main memory access continuation signal for controlling continuation of main memory access.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a central processing unit (CPU), 2 is a data bus,
3 is an address bus, and 4 is a command bus to which data read and write instructions are output. 5 is a main memory circuit composed of an inexpensive refresh memory (eg, dynamic RAM).

When CPU 1 instructs main memory circuit 5 to read or write data, a main memory access address is input from address bus 3 to address adder circuit 7 via address buffer 6 .

8 is a main memory access continuation signal when reading or writing continuous data, and 9 is an address addition signal 1 to the address addition circuit 7 by the main memory access command from the command bus 4 and the main memory access continuation signal 8.
This is a main memory access control circuit that outputs main memory access signals 11 such as a strobe signal for address 0 and the main memory circuit 5, a write instruction signal, and a data output instruction signal.

12 is a data buffer that controls data input/output when reading and writing data between the CPUI and the main memory circuit 5; 13 is an address signal output from the address addition circuit 7 to the main memory circuit 5; It is.

Next, the operation of the present invention will be explained using a timing chart.

FIG. 2 is a timing chart when reading data. The zero timing chart is an example when reading 10 consecutive words of data.

20 is the basic clock of the CPUI. At the SO stage, the CPU sends an address AO to the address bus 3 and a command C to read an arbitrary number of data onto the command bus 4.
Output RO. At the same time, the main memory access continuation signal 8 is made active (“H”).

The main memory access control circuit 9 receives an address strobe signal 11 from the command CRO and the main memory access continuation signal 8.
a and the data output instruction signal 11b from the 81st stage.
It activates up to 10 stages and outputs it to the main memory circuit 5.

Then, the address output 13 from the address addition circuit 7 is outputted by the address addition signal 10 to AO,
Al...A9, and the corresponding read data RDO-
- RD9 is output to data bus 2.

FIG. 3 is a timing chart when writing data, and is an example in which 10 words of data are written continuously.

At the SO stage, the CPU outputs an address AO onto the address bus 3 and a command CWO to write an arbitrary number of data onto the command bus 4. At the same time, the main memory access continuation signal 8 is made active (“H”).

The main memory access control circuit 9 sends an address strobe signal 11a and a write instruction signal 11c to the main memory circuit 5.
Output between l and SIO stages and output power dress addition circuit 7
The address addition signal 10 is output to.

As a result, the address output 13 becomes AO to A9, and write data WDO to WD9 are written to consecutive addresses.

〔Effect of the invention〕

As explained above, the present invention provides an address addition circuit that adds main memory access addresses, and uses a read/write command for an arbitrary number of data in consecutive addresses and a main memory access continuation signal to control the main memory circuit address strobe. By outputting a signal, a write instruction signal, a data output instruction signal, etc. for the required number of cycles and using the dynamic RAM page access method, it is possible to read and write arbitrary continuous data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart when reading data, and FIG. 3 is a timing chart when writing data. 1... Central processing unit f (CPU), 2... Data bus, 3... Address bus, 4... Command bus, 5
...Main memory circuit, 6...Address buffer, 7...
- Address addition circuit, 8... Main memory access continuation signal, 9... Main memory access control circuit, 10... Address addition signal, 11... Main memory access signal, lla.
...address strobe signal, llb...data output instruction signal, llc...data write instruction signal, 12.
・Data buffer, 13...address output signal.

Claims (1)

[Claims] an address addition circuit provided between a central processing unit and a main memory circuit to sequentially add main memory access addresses from the central processing unit; and a main memory for accessing an arbitrary number of data with consecutive addresses. It is characterized by comprising means for sequentially reading data from the main memory access address and means for sequentially writing data in response to a command and a main memory access continuation signal that controls continuation of main memory access by the main memory command. Memory control circuit.