JPH04155841A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to stabilize easily the form of a recess by a method wherein a dielectric dummy gate and a dielectric dummy recess are provided, the dummy gate and the dummy recess are selectively etched away by a wet etching method and a recess region is formed. CONSTITUTION:A dielectric dummy gate 2, which has a width identical with a gate length and is thicker than the depth of a recess, is formed on a semiconductor active layer 1. A dielectric layer 3b is evenly laminated from the direction vertical to the gate 2. The dielectric layer 3b is etched by an RIE method and a dummy recess 3a is formed. An N<+> semiconductor layer 4 is selectively grown at a place, from where the dielectric layer 3b is removed. A photoresist 5 is applied on the whole surface and the tip part of the gate 2 is made to expose by an etchback or the like. The position of a gate is aligned. The gate 2 and the recess 3a are selectively etched away by a wet etching method and a recess region 6 is formed. Gate electrode metal films 7a and 7b are laminated on the whole surface. Unnecessary gate electrodes 7b and the resist 5 are removed and a gate electrode 7a is formed in the region 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a method for manufacturing a semiconductor device.

[Conventional technology]

FIGS. 3(a) to 3(C) are cross-sectional views showing each step of a conventional semiconductor device manufacturing method. In the figures, 1 is a semiconductor active layer, 4 is an n++ conductor layer laminated on the active layer l, and 8 .9 is a source/drain ohmic electrode formed on the n''' semiconductor layer 4; 5 is a photoresist; 6 is a recess region where the n+ type half layer 4 is formed; 7 is a recess region formed within the recess region 6. This is a Schottky gate electrode.

Next, a method of manufacturing the conventional semiconductor device shown in FIG. 3 will be explained. As shown in FIG. 3fa), a semiconductor active layer 1,
After forming the n3 type semiconductor layer 4 and the source/drain ohmic electrodes 8 and 9, a photoresist 5 is applied to the entire surface and an opening is formed by photolithography. Next, Figure 3(b)
As shown in FIG. 3, a recess region 6 is formed by wet etching to a desired depth while monitoring the current between the source and drain of the n+ type half layer 4 using the photoresist 5 as a mask. Next, a gate electrode metal 7 is deposited on the entire surface by a vacuum evaporation method or the like, and unnecessary photoresist 5 and gate electrode metal are removed by a lift-off method to complete a semiconductor device as shown in FIG. 3(C).

[Problem to be solved by the invention]

Conventional semiconductor device manufacturing methods have the above-mentioned structure, which causes problems such as variations in the amount of etching when forming recess regions, large variations in recess shape between wafers and within the wafer surface, and unstable device performance. There was.

This invention has been made to solve the above-mentioned problems, and a first object of the invention is to provide a method for manufacturing a semiconductor device that can easily stabilize the recess shape.

A further object of the second invention is to provide a method for manufacturing a semiconductor device that can stabilize the recess shape and easily form an offset gate in the recess.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to a first aspect of the present invention is to provide a dielectric dummy gate for gate position alignment and a dielectric dummy recess corresponding to a recess shape in advance on a semiconductor active layer, selectively grow an n++ semiconductor, A photoresist is applied to the entire surface and the tip of the dummy gate is exposed by etchback, and then the dummy gate and dummy recess are selectively etched away by wet etching to form a recessed area. .

Furthermore, in the method of manufacturing a semiconductor device according to the second invention, a dielectric dummy gate for gate position alignment and a dielectric dummy recess are provided in advance on the semiconductor active layer so that the drain side is larger than the source side.
Selectively grow the semiconductor, apply photoresist to the entire surface, and etch back to expose the tip of the dummy gate.
Thereafter, the dummy gate and the dummy recess are selectively etched away by wet etching to form a recess region and an offset gate having a wide drain side.

[Effect]

In the method for manufacturing a semiconductor device according to the first invention, the gate position is aligned by a dielectric dummy gate, and the recess shape is determined by the dielectric dummy recess during epitaxial growth.

In the method for manufacturing a semiconductor device according to the second invention, the gate position is aligned by the dummy gate, the recess shape is determined during epitaxial growth by the dielectric dummy recess, and the dummy recess shape is wide on the drain side, so that the offset gate in the recess is It is formed.

〔Example〕

Hereinafter, embodiments of the first invention will be described with reference to the drawings. 1st
In the figure, 10 is a semiconductor substrate, and 1 is the semiconductor substrate 10.
A semiconductor active layer laminated thereon, 2 a dielectric dummy gate formed on the semiconductor active layer 1, 3 a a dielectric dummy recess, 3 b a dielectric for forming the dummy recess, 4 selectively grown after the dummy recess is formed; Tan Imao conductor layer, 5
6 is a photoresist layer, 6 is a recessed region formed by etching away the dummy recess and dummy gate 2, and 7 is a photoresist layer.
A is a gate electrode formed in the recess region 6, and 7b is a gate electrode metal.

Next, a method for manufacturing a semiconductor device according to the first invention shown in FIGS.

As shown in FIG. 1(a), a dielectric dummy gate 2 having a width equal to the gate length and thicker than the recess depth is formed on the semiconductor active layer l.

Next, as shown in FIG. 1 (bl), dielectrics 3b for forming dummy recesses 3a are stacked uniformly in the vertical direction.

At this time, the etching rate for reactive ion etching (hereinafter referred to as RIE) is increased by changing the growth conditions for the dielectric of the dummy gate 2.

Next, as shown in FIG. 1(C), the dielectric material 3b is
etching. At this time, dummy gate 2 and dielectric 3
A dummy recess 3a is formed due to the difference in etching rate b.

Next, as shown in FIG. 1(d), an n1 type semiconductor layer 4 is selectively grown in the area where the dielectric 3b has been etched away.

Next, as shown in FIG. 1(e), photoresist 5 is applied to the entire surface.
, and expose the tip of the dummy gate by etching back, etc. This allows the gate positions to be aligned.

Next, as shown in Figure 1), the dummy gate 2 and the dummy recess 3a are selectively etched away by wet etching to form a recess region 6.

Next, as shown in FIG. 1(g), gate electrode metals 7a and 7b are laminated over the entire surface by vacuum evaporation or the like. Next, unnecessary gate electrode 7b and photoresist 5 are removed by a lift-off method, and gate electrode 7a is formed in recessed region 6 as shown in FIG.

In this embodiment of the invention in Section 1, the gate position is aligned using the dielectric dummy gate, and the recess shape is determined during epitaxial growth using the dielectric dummy recess, so the controllability of the recess shape is improved and the device characteristics are stabilized. You can get the effect of

Next, an embodiment of the second invention will be described with reference to the drawings. Second
In the drawings, numerals 1 to 7 are the same as FIG. 1 showing an embodiment of the first invention, and the method of manufacturing a semiconductor device according to the second invention shown in FIGS. 2(a) to 2 will be described below.

As shown in FIG. 2(a), a dielectric dummy gate 2 is formed on the semiconductor active layer 1 with the same width as the gate length and thicker than the recess depth.

Next, as shown in FIG. 2(b), dielectrics 3b for forming dummy recesses 3a are stacked uniformly in the vertical direction.

At this time, the etching rate for RIE is increased by changing the growth conditions for the dielectric of the dummy gate 2 (.

Next, as shown in FIG. 2(C), dielectrics 3c, which are the same as dielectrics 3b, are stacked diagonally from the drain side to make the dielectric on the drain side thicker.

Next, as shown in FIG. 2(d), the dielectric material 3b is
, etching 3c. At this time, a dummy recess 3a having a shape as shown in FIG. 2(d) is formed due to the difference in etching rate between the dummy gate 2 and the dielectrics 3b and 3c and the dielectric 3C.

Next, as shown in FIG. 2(e), the n+ type half body layer 4 is selectively grown.

Next, as shown in Figure 2), apply photoresist 5 on the entire surface.
, and expose the tip of the dummy gate 2 by etching back or the like. This aligns the gate positions.

Next, as shown in FIG. 2(g), the dummy gate 2 and the dummy recess 3a are selectively etched away by wet etching to form a recess region 6.

Next, as shown in FIG. 2(h), gate electrode metals 7a and 7b are laminated over the entire surface by vacuum evaporation or the like.

Next, unnecessary gate electrode metal 7b and photoresist 5
is removed by the lift-off method, as shown in Figure 2 (i),
A gate electrode 7a is formed within the recess region 6, forming an offset gate within the recess.

In such an embodiment of the second invention, the gate position is aligned by the dummy gate, the recess shape is determined during epitaxial growth by the dielectric dummy recess, and the dummy recess shape is wide on the drain side, so the recess shape is Controllability is improved, source parasitic resistance R1 is reduced by offset gate in the recess,
The effect of improving the drain breakdown voltage V x d6 can be obtained.

〔Effect of the invention〕

As described above, according to the first invention, a dielectric dummy gate for gate position alignment and a dielectric dummy recess corresponding to the recess shape are provided in advance on the semiconductor active layer,
After selectively growing an n+ type semiconductor, coating the entire surface with photoresist, and exposing the tip of the dummy gate by etching, etc., the dummy gate and the dummy recess are etched away by sea urchin dot etching, and the recess area is removed. , the controllability of the recess shape is improved and the device performance is stabilized.

Furthermore, according to the second invention, a dielectric dummy gate for gate position alignment and a dielectric dummy recess are provided in advance on the semiconductor active layer so that the drain side is thicker than the source side, and selective growth of the n+ type semiconductor is performed. After applying photoresist to the entire surface and exposing the tip of the dummy gate by etching back, etc., the dummy gate and the dummy recess are removed by wet etching to form a recess area, and the dummy gate is removed by wet etching. Since the offset gate within the wide recess is formed, controllability of the recess shape is improved, the source parasitic resistance Rg is reduced by the offset gate within the recess, and the train breakdown voltage Vgdo is improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of each step showing a method for manufacturing a semiconductor device according to an embodiment of the first invention, and FIG. 2 is a cross-sectional view of each step showing a method of manufacturing a semiconductor device according to an embodiment of the second invention. 3
The figure is a cross-sectional view showing each step of a conventional method for manufacturing a semiconductor device. 1 is a semiconductor active layer, 2 is a dielectric dummy gate, 3a is a dielectric dummy recess, 4 is an n + type semiconductor layer, 5 is a photoresist, 6 is a recess region, 7 is a gate electrode, and 8 and 9 are source and drain electrodes. . Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (2)

[Claims] (1) The process of providing in advance on the semiconductor active layer a dielectric dummy gate with the same width as the gate length and thicker than the recess depth for gate position alignment, and a dielectric dummy recess corresponding to the recess shape, and a high impurity concentration semiconductor layer. selectively growing the dummy gate, coating the entire surface with photoresist, and exposing the tip of the dummy gate by etching back, etc., and selectively etching away the dummy gate and dummy recess by wet etching to remove the recessed area. 1. A method of manufacturing a semiconductor device, comprising the step of forming a semiconductor device. (2) A dielectric dummy gate with the same width as the gate length and thicker than the recess depth for gate position alignment on the semiconductor active layer, and a dielectric dummy recess corresponding to the recess shape so that the drain side is larger than the source side. selectively growing a high impurity concentration semiconductor layer, coating the entire surface with photoresist and exposing the tip of the dummy gate by etching back, etc., and forming the dummy gate and dummy recess by wet etching. 1. A method of manufacturing a semiconductor device, comprising the steps of selectively etching away, forming a recess region, and forming a wide offset recess gate on the drain side.