JPH01202868A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To control the thickness of an active layer easily, and to reduce the dispersion of characteristics such as a threshold by composing a high- concentration semiconductor layer for lowering source resistance of proper two layers. CONSTITUTION:A high-concentration semiconductor layer for lowering source resistance is constituted of two layers 5, 6, and a lower layer (the first high- concentration semiconductor layer 5) in them is shaped by a material different from active layers 3, 4. Consequently, selective wet etching can be applied when a gate electrode 17 forming section is removed, and etching is not conducted up to the active layers when the first high-concentration semiconductor layer 5 is etched. Accordingly, the layer thickness of the active layers under a gate electrode 17 can be controlled accurately, thus reducing the dispersion of characteristics such as threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor (FET) and a method of manufacturing the same, and particularly to a Schottky gate field effect transistor (MESFET) and a method of manufacturing the same.

[Conventional technology]

In FETs in which the active layer is formed by epitaxial growth, it is known to provide an n+ layer between the source electrode and the active layer in order to reduce source resistance. To manufacture such a FET, after forming an n+ layer on the active layer, the n+ layer in the gate electrode formation area is removed, and the gate electrode is formed on the active layer, and the source and drain electrodes are formed on the n+ layer. This is done by vapor deposition.

[Problem to be solved by the invention]

However, when removing the n layer in the gate electrode formation area,
The use of dry etching techniques has the problem of causing significant damage to the active layer and changes in stoichiometry. Furthermore, when wet etching technology is used, the active layer is etched, making it difficult to control its thickness, which causes variations in characteristics such as the threshold value of the FETs fabricated.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the FET of the present invention includes an active layer formed by epitaxial growth, and a first high concentration semiconductor layer formed on the active layer and having a different material and the same conductivity type as the active layer. and removing a second high concentration semiconductor layer having the same material and conductivity type as the active layer and formed on the first high concentration semiconductor layer, and the first and second high concentration semiconductor layers. A gate electrode is formed on the exposed active layer, and a source electrode and a drain electrode are respectively formed on the second high concentration semiconductor layer on both sides of the gate electrode. Furthermore, it is preferable that the gate electrode has a shape whose upper part is widened, or that the active layer has a two-layer step-doped structure.

Further, the manufacturing method of the present invention includes forming a first high concentration semiconductor layer having a different material and the same conductivity type as the active layer on the active layer formed by epitaxial growth; forming a second high concentration semiconductor layer having the same material and conductivity type as the active layer on the active layer;
forming a source electrode and a drain electrode in predetermined regions on the high concentration semiconductor layer; a step of selectively wet etching the first highly doped semiconductor layer using an etchant that does not etch the second highly doped semiconductor layer after removing the doped semiconductor layer by dry etching; The method includes a step of forming a gate electrode on the active layer exposed by wet etching.

[Effect]

The high concentration semiconductor layer for reducing source resistance is composed of two layers, the lower layer of which (first high concentration semiconductor layer)
Since the material is different from that of the active layer, selective etching can be applied to remove the gate electrode forming portion. That is, when etching the first high concentration semiconductor layer, the active layer is not etched. Moreover,
Since the first high concentration semiconductor layer is etched by wet etching, it does not damage the active layer or change the stoichiometry.

Further, when the upper part of the gate electrode is expanded, the gate resistance does not increase even if the gate length is shortened to the micron order. Furthermore, if the active layer has a two-layer structure, mainly FE
The lower active layer that determines the characteristics of T can be protected by the upper layer, and the gate breakdown voltage is improved because the upper layer has a low impurity concentration.

[Example] FIG. 1 is a process cross-sectional view showing an example of the present invention, and FIG. 1 (I) shows the cross-sectional structure of an FET manufactured as a result of these manufacturing steps.

First, on a semi-insulating GaAs substrate 1, a p-GaAs layer 2, an n''-GaAs layer 3, an n--GaAs
The s-layer 4, the n-AJGaAs layer 5, and the n-GaAs layer 6 are epitaxially formed in this order. Among these epitaxial layers, the p-GaAs layer 2 is a layer for suppressing short channel effects. n”-GaAs layer 3 and n”--GaAs
Layer 4 is an active layer, and by forming the active layer into a two-layer step-doped structure, the lower n-GaAs layer 3, which mainly determines the characteristics of the FET, is replaced by n-GaAs layer 3, which will be described later.
- protects the GaAs layer 6 from etching;
Gate breakdown voltage can be improved. n-Aj7
The GaAs layer 5 and the n-GaAs layer 6 are layers for reducing the source resistance of the FET and have a two-layer structure, so a desired active layer can be obtained under the gate electrode by going through the steps described below. Can be done. (Figure 1 (A))
.

Next, a resist is applied on the n-GaAs layer 6 to form a lower resist layer 7, and an S I O2 film 8 is formed on it.
After depositing resist, resist is applied again to form an upper resist layer 9. Then, the upper resist layer 9 is patterned into a gate electrode pattern using a normal photolithography technique (FIG. 1(B)).

Next, the SiO2 film 8 is selectively etched by reactive ion etching (RIE) using CF4+H2 gas using the patterned upper resist layer 9 as a mask, and the lower resist layer 7 is further etched by RIE using O2 gas. Select and etch. At this time, since the lower resist layer 7 is etched to a deeper extent than the S 102 film 8, an undercut portion 11 is formed. Further, since the upper resist layer 9 is also removed at the same time when the lower resist layer 7 is etched, a T-shaped dummy gate 10 consisting of the SiO2 film 8 and the lower resist layer 7 is formed. Note that the length of the undercut portion 11 can be adjusted to some extent by adjusting the film thickness of the lower resist layer 7, and in this example, an undercut of about 0.2 μm on one side and 0.4 μm in total is made (the Figure 1 (C)).

Next, S 102 is applied to the entire surface including the dummy gate 10.
After depositing Ml 2 (FIG. 1(D)), the dummy gate 10 is lifted off to obtain the Sio 2 film 12 from which the underlying pattern of the dummy gate 10 has been removed. Then, a resist film 13 is formed thereon, and a pattern in which the source/drain electrode (ohmic electrode) formation region is removed is formed using a normal photolithography technique (see FIG. 1).
E)).

Next, using the resist film 13 as a mask, SiO is deposited by RIE.
After etching the second film 12, an ohmic metal is deposited on the surface. Then, by lifting off the resist film 13, a source electrode 14 and a drain electrode 15 are formed (FIG. 1(F)).

Next, resist is again applied to the entire surface to form a resist film 16, and a gate pattern is formed by photolithography. The gate pattern at this time is the same as the gate pattern used when forming the dummy gate 10. After that, using the resist film 16 and the SiO2 film 12 exposed in the gate pattern of the resist film 16 as a mask, the reaction gas was CC]2F2+He.
GaAs layer 6 is selectively dry etched.

At this time, the n -GaAs layer 6 penetrates inside and is etched, so the film edge 2 of the SiO2 film 12 is n -
It protrudes from the end surface of the GaAs layer 6 and forms an eaves portion (
Figure 1 (G)).

Next, the n-AjpGaAs layer 5 is wet-etched using KI:122H20 as an etchant. At this time, since the n--GaAs layer 4, which is the active layer, is not etched with this etchant, n-A
Selective wet etching of the IIGaAs layer 5 can be achieved (FIG. 1(H)).

Finally, a gate metal is deposited and the resist film 16 is lifted off to form a gate electrode 17, thereby completing the transistor. Note that since the vapor deposition on the surface of the +-GaAs layer 6 is regulated by the eaves of the SIO2 film 12, the gate length is approximately equal to the distance between the eaves of the SiO2 films 12 facing each other. Therefore, the gate length is shorter than the gate length of the gate pattern used when forming the dummy gate 10. Further, the upper part of the main SiO2 film 12 has a length equal to the gate pattern provided on the resist film 16.

In this example, the SiO2 film 12 is used as a layer for regulating the gate length, but other etching methods may be used if the selective etching of the ohmic region performed from FIGS. 1(E) to 1(F) is possible. Materials may be used.

Further, although a transistor using GaAs for the active layer is taken as an example, the present invention can also be applied to a transistor using other semiconductors, such as InP for the active layer.

〔Effect of the invention〕

As explained above, according to the FET and its manufacturing method of the present invention, the high concentration semiconductor layer for reducing the source resistance is composed of two appropriate layers, so the first high concentration semiconductor layer is etched. When exposing the gate electrode forming portion of the active layer, the active layer is not etched. Therefore, the layer thickness of the active layer under the gate electrode can be strictly controlled, and as a result, variations in characteristics such as threshold voltage can be made extremely small. Further, since wet etching is used to expose the gate electrode forming portion of the active layer, the active layer is not damaged or its stoichiometry is changed, and the characteristics can be stabilized in this respect as well.

Furthermore, if the upper part of the gate electrode is expanded, the gate resistance can be kept low, and if the active layer has a two-layer structure, at least The lower active layer can be protected, and the gate breakdown voltage can be improved due to the presence of the upper active layer.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the present invention. 1... Semi-insulating GaAs substrate, 2-.p-GaAs layer, 3-n''-GaAs layer, 4-n--GaAs layer, 5-
= n”-AIGaAs layer, 6-n
-GaAs layer, 7...lower resist layer, 8...Si
O2 film, 9... Upper resist layer, 10... Dummy gate, 11... Undercut portion, 12... Si
O2 film, 14...source electrode, 15...drain electrode, 16...resist film. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Tatsuya Process cross-sectional view of the embodiment Figure 1 Process cross-section diagram of the example Example Process cross-sectional view Figure 1 Process cross-section diagram of the example Example Figure 1

Claims (1)

[Scope of Claims] 1. an active layer formed by epitaxial growth, a first high concentration semiconductor layer formed on this active layer and having a different material and the same conductivity type as this active layer, and the active layer a second high-concentration semiconductor layer having the same material and conductivity type as the first high-concentration semiconductor layer and the second high-concentration semiconductor layer exposed by removing the first and second high-concentration semiconductor layers; A field effect transistor having a gate electrode formed on an active layer, and a source electrode and a drain electrode formed on the second high concentration semiconductor layer on both sides of the gate electrode. 2. The field effect transistor according to claim 1, wherein the upper part of the gate electrode is widened. 3. The field effect transistor according to claim 1 or 2, wherein the active layer has a two-layer structure, and the impurity concentration in the upper layer is lower than that in the lower layer. 4. On the active layer formed by epitaxial growth, a first high-concentration semiconductor layer having a different material and the same conductivity type as this active layer is formed, and further, on the first high-concentration semiconductor layer, the active layer and forming a second high concentration semiconductor layer having the same material and conductivity type; forming a source electrode and a drain electrode in predetermined regions on the second high concentration semiconductor layer; After removing the second high concentration semiconductor layer by dry etching using a suitable film with a gate electrode pattern formed on the concentration semiconductor layer as a mask, the first high concentration semiconductor layer is removed as a second high concentration semiconductor layer.
selective wet etching using an etchant that does not etch the second high concentration semiconductor layer; and forming a gate electrode on the active layer exposed by the wet etching of the second high concentration semiconductor layer. Production method.