JPH1167791A - Junction field-effect transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively reduce the gate length by making the length of a semiconductor barrier layer in the gate length direction shorter than the gate length of a gate electrode. SOLUTION: A barrier (ALGaAs) layer 4 provided at a lower part of a T-type gate electrode 5 to raise the gate breakdown voltage has a longer length in the gate length direction than the gate length of the electrode 5. A negative bias is applied to the gate electrode 5 to expand a depletion layer to control the current flowing in a channel (n-GaAs 3) region in a gate electrode 5 lower part. By reducing the length of the AlGaAs layer 4 more than the gate length, the effective gate length can be made short by limiting it to the length of the layer 4, even if the gate electrode length is the same. Thus it is possible to reduce the effective gate length even in a submicron range difficult to reduce the length of the gate electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a reduced gate length, and more particularly to a structure of a junction field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 is a cross-sectional view showing an example of a conventional junction field effect transistor. In FIG. 6, 1 is a GaAs substrate, 2 is a buffer layer, 3 is an n-GaAs layer, and 4 is AlG
The aAs layer, 5 indicates a gate electrode, 6 indicates a source electrode, 7 indicates a drain electrode, and 8 indicates a recess. As shown in FIG. 6, in the conventional junction field effect transistor, the gate electrode 5 and n
By forming an AlGaAs layer 4 having a smaller electron affinity and a larger band gap than the n-GaAs layer 3 between the n-GaAs layer 3 and the GaAs layer 3, the Schottky barrier between the gate electrode and the semiconductor is increased, and the gate breakdown voltage is reduced. The withstand voltage is increased (Japanese Patent Application Laid-Open No. 4-2067334).

[0003]

The gate electrode of the junction field effect transistor shown in FIG. 6 is formed by embedding an electrode material in a side wall (not shown) formed so as to cover the side wall of the recess 8. Although the gate length was controlled by the thickness of the sidewall, it was difficult to control the gate length in a submicron region. Therefore, as a result of intensive research, the inventor has found that the AlGaAs layer 4 provided to increase the gate breakdown voltage of the junction field-effect transistor,
By optimizing the etching conditions, selective etching can be performed with good control. By etching the length of the AlGaAs layer 4 in the gate length direction shorter than the gate length of the gate electrode 5 formed thereon, the gate of the gate electrode 5 can be etched. It has been found that the gate length can be substantially reduced even if the length is the same as the conventional one. That is, the present invention
It is an object of the present invention to provide a junction field-effect transistor with an effectively shortened gate length.

[0004]

The inventors of the present invention have conducted intensive studies and found that the Al under the gate electrode provided to increase the gate breakdown voltage of the junction field effect transistor.
Utilizing a GaAs layer, only the AlGaAs layer is selectively etched, and the AlGa than the gate length of the gate electrode is used.
The inventors have found that by reducing the length of the As layer in the gate length direction, it is possible to shorten the effective gate length even if the gate length of the gate electrode is the same as in the related art, and completed the present invention.

That is, the present invention provides a semiconductor device of the second conductivity type having a smaller electron affinity and a larger band gap than a semiconductor layer of a first conductivity type provided on a semiconductor substrate provided on a semiconductor substrate. A gate electrode provided via a semiconductor barrier layer of a first conductivity type; and a depletion layer extending from the gate electrode into the semiconductor layer of the first conductivity type via the semiconductor barrier layer, the first electrode sandwiching the gate electrode. A junction field-effect transistor for controlling current between a source electrode and a drain electrode provided on a conductive semiconductor, wherein the length of the semiconductor barrier layer in the gate length direction is larger than the gate length of the gate electrode. This is a junction field-effect transistor characterized by being short. As described above, in order to increase the gate breakdown voltage of the junction field-effect transistor, the semiconductor barrier layer provided under the gate electrode is selectively etched, and the semiconductor barrier layer is selectively etched so that the gate length direction is improved. By making the length of the gate electrode shorter than the gate length of the gate electrode, even if it is difficult to shorten the gate length of the gate electrode,
The effective gate electrode length can be shortened, and the characteristics of the junction field effect transistor can be improved.

The semiconductor barrier layer may be provided in a recess formed in the semiconductor layer of the first conductivity type.

The semiconductor barrier layer may be provided on the planar semiconductor layer of the first conductivity type.

The semiconductor layer of the first conductivity type is GaAs.
s, and the semiconductor barrier layer is preferably made of AlGaAs.

Further, the present invention provides a laminating step of sequentially laminating a semiconductor layer of a first conductivity type and a semiconductor barrier layer of a second conductivity type or an insulation type on a semiconductor substrate, and forming a gate on the semiconductor barrier layer. A gate electrode forming step of forming an electrode, and a selective etching step of selectively etching the semiconductor barrier layer so that the length of the semiconductor barrier layer in the gate length direction is shorter than the gate length of the gate electrode; Forming a source electrode and a drain electrode on the semiconductor layer of the first conductivity type so as to sandwich the gate electrode, respectively. By using such a method, a junction field effect transistor having a gate electrode that is effectively short utilizing a semiconductor barrier layer provided below the gate electrode in order to increase the gate breakdown voltage of the junction field effect transistor. This makes it possible to produce

The laminating step includes a step of covering a sidewall of the recess provided in the first conductive type semiconductor layer with a sidewall, and the step of forming the first conductive type semiconductor layer opened in the sidewall on the first conductive type semiconductor layer. Forming a semiconductor barrier layer, further comprising the step of: embedding a gate electrode material on the semiconductor barrier layer in the recess in the gate electrode forming step; and processing the gate electrode material to form a gate electrode. And a step of selectively removing the sidewalls after the formation. By using such a method, a junction field effect transistor having a short gate electrode length can be effectively manufactured using a semiconductor barrier layer provided below a gate electrode even in a junction field effect transistor having a recess. This is because

Further, according to the present invention, the semiconductor layer of the first conductivity type, the semiconductor barrier layer, and the gate electrode each include a G layer.
aSi, AlGaAs, WSi, and the selective etching step selectively etches only the semiconductor barrier layer using dilute hydrofluoric acid without etching the first conductivity type semiconductor layer and the gate electrode. The method is also a method for manufacturing a junction field effect transistor.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows a cross-sectional view of a junction field-effect transistor according to a first embodiment of the present invention. 6, the same reference numerals as those in FIG. 6 denote the same or corresponding parts. In the junction field effect transistor according to the present embodiment,
The AlGaAs layer 4 provided below the T-type gate electrode 5 to increase the gate breakdown voltage is formed such that the length in the gate length direction is shorter than the gate length of the gate electrode 5. In the junction field effect transistor, the current flowing through the n-GaAs 3 region (channel region) below the gate electrode 5 is controlled by applying a negative bias to the gate electrode 5 to extend the depletion layer, as shown in FIG. AlGaA
By making the length of the s layer 4 shorter than the gate length, the effective gate length can be shortened by limiting the length of the AlGaAs layer 4 even if the length of the gate electrode 5 itself is the same. It becomes possible. Therefore, even in the submicron region where it is difficult to shorten the gate length of the gate electrode 5 itself, the effective gate length can be reduced, and the element characteristics of the junction field effect transistor can be improved. .

Next, a method of manufacturing the junction field effect transistor according to the embodiment of the present invention shown in FIGS. 2 and 3 will be described. First, an n-GaAs layer 3 is formed on a semiconductor substrate 1 via a buffer layer 2 and a source electrode 6 and a drain electrode 7 are formed at predetermined positions, respectively, as shown in FIG. Next, the n-GaAs 3 is etched by RIE or the like using the insulating film 9 such as SiN as a mask to form a recess 8. Next, as shown in FIG. 2B, the entire surface including the side surface of the recess 8 is formed by using the CVD method.
An iO ₂ insulating film is deposited (not shown), followed by ECR plasma etching or ICP (Induced Coupled Plasma).
The SiO ₂ insulating film is etched from above using etching, and the SiO ₂ insulating film is left only on the side wall of the recess 8 to form the sidewall 10. Next, as shown in FIG. 2C, the AlGaAs layer 10 is selectively grown on the bottom of the recess 10 by using the sidewall 10 as a mask by a chemical beam epitaxy (CBE) method or an MOCVD method. Next, as shown in FIG. 2D, after a gate electrode material such as WSi is formed on the entire surface by sputtering, the T-type gate electrode 5 is formed by etching using a resist mask (not shown). I do. Next, as shown in FIG. 3E, the sidewalls 10 are removed by etching with buffered hydrofluoric acid. Finally, using diluted hydrofluoric acid, A
The lGaAs layer 4 is side-etched. By using such diluted hydrofluoric acid, only the AlGaAs layer 4 can be selectively etched without etching the gate electrode 5 and the n-GaAs layer 3, and the etching rate is 10 ° / sec. Degree,
The length of the n-GaAs layer 3 can be controlled with high accuracy. As described above, by using the manufacturing method according to this embodiment, the junction field-effect transistor shown in FIG. 1 can be manufactured.

Embodiment 2 FIG. FIG. 4 is a cross-sectional view of a junction field-effect transistor according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 6 denote the same or corresponding parts, and 11, 12, and 13 denote n-GaAs layers, n'-GaAs regions, and n ⁺ -GaAs formed by ion implantation.
Each area is shown. The junction field-effect transistor according to this embodiment is obtained by applying the structure of the first embodiment to a planar junction field-effect transistor. As in the first embodiment, the gate electrode 5 itself is formed. AlG even in the submicron region where it is difficult to shorten the gate of
By making the length of the aAs layer 4 shorter than the gate length, the effective gate length can be shortened, and the element characteristics of the junction field effect transistor can be improved.

Next, a method of manufacturing a planar junction field effect transistor according to the embodiment of the present invention shown in FIG. 5 will be described. First, as shown in FIG.
An n-GaAs layer 11 is formed on the semiconductor substrate 1 by injecting Si by an ion implantation method.
As shown in (b), the AlGaAs layer 4 is grown by using the CBE method or the MOCVD method. Next, as shown in FIG. 5C, a WSi film or the like is formed by a sputtering method, patterning is performed using a resist mask (not shown) or the like, and a gate electrode 14 is formed. The AlGaAs layer 4 is etched as a mask, and the gate electrode 14 is etched.
The AlGaAs layer 4 is left just below. Next, FIG.
As shown in FIG. ₂ , a SiO ₂ insulating film (not shown) is deposited on the entire surface by the CVD method, and then the SiO ₂ insulating film is etched from above by the ECR plasma etching method or the ICP etching method, and the side wall of the gate electrode 14 is formed. The sidewall 15 is formed only on the substrate. Subsequently, the n′-GaAs layer 12 is formed by ion implantation using the gate electrode 14 and the sidewalls 15 as a mask. Next, FIG.
As shown in (e), after depositing the SiO ₂ insulating film 16 on the entire surface by using the CVD method, n is again formed by the ion implantation method.
^{A +} -GaAs layer 13 is formed. Next, as shown in FIG. 5F, after the SiO ₂ insulating film 16 is removed by etching with buffered hydrofluoric acid, AlGa is removed using dilute hydrofluoric acid.
The As layer 4 is selectively side-etched to form an AlGaAs layer 4.
Is shorter than the gate length. Finally, after the source / drain electrode material is deposited on the entire surface, the source / drain electrodes 6 and 7 are formed by etching. As described above, by using the manufacturing method according to this embodiment, the junction field-effect transistor shown in FIG. 4 can be manufactured. In such a junction field-effect transistor, as in the first embodiment, the length of the AlGaAs layer 4 is made shorter than the gate length, so that the effective gate is effective even if the gate electrode 5 itself has the same length. Length is AlG
The length can be reduced by limiting the length of the aAs layer 4, and the device characteristics of the junction field effect transistor can be improved.

[0016]

As is apparent from the above description, the junction field effect transistor according to the present invention utilizes the semiconductor barrier layer provided below the gate electrode to increase the gate breakdown voltage. By selectively etching the semiconductor barrier layer so that the length in the gate length direction is shorter than the gate length of the gate electrode, the gate length can be effectively reduced, and the characteristics of the junction field effect transistor can be reduced. Can be improved. In particular, even in a submicron region where the processing of the gate electrode is difficult, the gate length can be substantially reduced without processing the gate electrode itself.

The present invention is also applicable to a semiconductor barrier layer provided in a recess formed in a semiconductor layer of the first conductivity type or on a planar semiconductor layer of the first conductivity type. It is possible to improve the characteristics of the transistor.

Further, by using the method according to the present invention, the gate electrode can be made effective by utilizing a semiconductor barrier layer provided below the gate electrode in order to increase the gate breakdown voltage of the junction field effect transistor. This makes it possible to manufacture a short junction field-effect transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a junction field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a manufacturing step of the junction field-effect transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing step of the junction field-effect transistor according to the first embodiment of the present invention;

FIG. 4 is a sectional view of a junction field-effect transistor according to a second embodiment of the present invention;

FIG. 5 is a cross-sectional view of a manufacturing step of the junction field-effect transistor according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional junction field-effect transistor.

[Description of Signs] 1 GaAs substrate, 2 buffer layer, 3 n-GaAs
Layer, 4 AlGaAs layer, 5 gate electrode, 6 source electrode, 7 drain electrode, 8 recess, 9 insulating film, 1
0 sidewall, 11 n-GaAs layer, 12
n′-GaAs region, 13 n ⁺ -GaAs region, 14
Gate electrode, 15 sidewall, 16 insulating film.

Claims (7)

[Claims] 1. A semiconductor barrier of a second conductivity type or an insulation type having a lower electron affinity and a larger band gap than a semiconductor layer of the first conductivity type on a semiconductor layer of the first conductivity type provided on a semiconductor substrate. A gate electrode is provided through a layer, and a semiconductor layer of the first conductivity type is sandwiched between the gate electrode by a depletion layer extending from the gate electrode through the semiconductor barrier layer into the semiconductor layer of the first conductivity type. A junction field effect transistor for controlling a current between a source electrode and a drain electrode provided on each of the above, wherein a length of the semiconductor barrier layer in a gate length direction is shorter than a gate length of the gate electrode. Junction field effect transistor. 2. The junction field effect transistor according to claim 1, wherein the semiconductor barrier layer is provided in a recess formed in the semiconductor layer of the first conductivity type. 3. The junction field effect transistor according to claim 1, wherein the semiconductor barrier layer is provided on the planar semiconductor layer of the first conductivity type. 4. The junction field effect transistor according to claim 1, wherein said first conductivity type semiconductor layer is made of GaAs, and said semiconductor barrier layer is made of AlGaAs. 5. A laminating step of sequentially laminating a semiconductor layer of a first conductivity type and a semiconductor barrier layer of a second conductivity type or an insulation type on a semiconductor substrate, and forming a gate electrode on the semiconductor barrier layer. A gate electrode forming step; a selective etching step of selectively etching the semiconductor barrier layer such that a length of the semiconductor barrier layer in a gate length direction is shorter than a gate length of the gate electrode; Forming a source electrode and a drain electrode on the semiconductor layer of the mold so as to sandwich the gate electrode, respectively. 6. A step of covering the side wall of the recess provided in the semiconductor layer of the first conductivity type with a sidewall, the step of laminating the semiconductor layer of the first conductivity type opened in the sidewall. Forming the semiconductor barrier layer, the gate electrode forming step further comprising: embedding a gate electrode material on the semiconductor barrier layer in the recess; and processing the gate electrode material to form a gate. 6. The method according to claim 5, further comprising the step of selectively removing the sidewall after forming the electrode. 7. The semiconductor device according to claim 1, wherein the semiconductor layer of the first conductivity type, the semiconductor barrier layer, and the gate electrode are GaAs, AlG, respectively.
aAs and WSi, wherein the selective etching step is a step of selectively etching only the semiconductor barrier layer using dilute hydrofluoric acid without etching the first conductivity type semiconductor layer and the gate electrode. 7. The method for manufacturing a junction field effect transistor according to claim 5, wherein: