JPS62154670A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To freely control gate recess width and improve DC and RF performance through selection of covered layer width by controlling gate recess region to the width corresponding to previously formed covered layer width. CONSTITUTION:A first resist layer 6 is formed in the width corresponding to the desired gate recess width to the desired position on the Si3N4 layer 5 of so-called channel region between the drain electrode 3 and source electrode 4, the Si3N4 layer 5 is selectively etched with such first resist layer 6 used as the mask and thereafter the Si3N4 layer pattern is formed as the first covered layer 5 in the width corresponding to the selective recess width on the semiconductor layer 2 between the drain electrode 3 and source electrode 4 by removing the first resist layer 6. With the second resist layer used as the mask, the semiconductor layer 2 is etched to the specified depth through an aperture to form the recess region 8 in the width corresponding to the pattern width of first covered layer 5. A gate electrode 9 material such as aluminum is deposited and the recess gate structure where the Schottky barrier gate electrode 9 is selectively formed in the recess region 8 can be obtained by applying the liftoff method.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for manufacturing a Fi field effect transistor, and particularly relates to a method for manufacturing a field effect transistor having a recessed gate structure.0 [Prior Art J Single crystal In IAAs field effect transistors (GaAs MES FETs) that use gallium arsenide (GaAa) as a semiconductor substrate or have a process gate structure, controlling the recess width is essential for improving DC and RF performance, and especially for Schottky transistors. Controlling the width of the bottom surface of the recess on which the gate electrode is deposited is extremely important.

Figure 2 shows a conventional John de pariah gate of this type.
The schematic structure of an example of a MES FET is shown. In the case of this conventional example, a semiconductor layer (12) serving as a channel layer is formed on a semi-insulating GaAs substrate (11) by vapor phase epitaxial growth or the like, and a drain (13) and a source are formed on the surface of this semiconductor layer (12). (14) Ohmink electrodes are formed at predetermined intervals. (See Figure 2 (a))
Subsequently, a resist layer (15) is formed which has openings at desired positions of the so-called channel head between the drain electrode (13) and the source electrode (14) and covers the pond. (Second
(See Figure (b)) Next, using the resist layer (15) as a mask, a concave part (16), a so-called recessed part, is formed in the semiconductor layer (12), and then a gate electrode such as aluminum (16) is formed by a well-known vacuum evaporation method. Apply material (17) (second
(See Figure (C)) After that, the Schottky barrier gate electrode (17) is formed in the recess (16) by applying the 7-7 method.
) to obtain a cess gate structure.

However, in this method, the recess order * (1
Since the width of 6) is uniquely determined by the recess depth and the amount of side etching corresponding to the recess depth, it is not possible to control the recess width to an arbitrary size, which determines the thickness of the semiconductor layer (12). . Therefore, when the thickness of the semiconductor layer (12) changes significantly, the recess width deviates from the appropriate range and De, Rr
There may be cases where significant deterioration of 4i performance is unavoidable.

In order to solve this problem, a method shown in the schematic configuration shown in FIGS. 3(a) to 3(a) has been adopted.

In this method, a semiconductor layer (22) that will become a channel layer is formed on a semi-insulating substrate (21) by vapor phase epitaxial growth or the like, and a drain (23) and a source are formed on the surface of this semiconductor layer (22). (24) Ohmink electrodes are formed at predetermined intervals. (See Figure 3(a)) Next, the drain electrode (23) and the source electrode (24)
A thin film (25) of silicon nitride or the like is formed on the entire surface of the semiconductor layer (22) by plasma CVD or the like (~zoooX
). (See Figure 3(b)) Next, an opening is formed at a desired position on the so-called channel Suzaka silicon nitride thin film (25) between the drain electrode (23) and the source electrode (24). A covering resist layer (26) is formed. (See Figure 3(c)) Next, using the resist layer (26) as a mask, the silicon nitride thin film (25) is selectively etched, and the resist layer (26) is etched to the inside of the opening in an appropriate manner and corresponding to the groove width. The side is etched to the point where it is exposed.

(See Figure 3 (d) > a) Using the resist layer (26) and the silicon nitride thin film (25) as masks, the semiconductor layer (
A recess (27), a so-called recessed slope, is formed in 22). (Fig. 3 (e)) After that, a gate electrode material such as aluminum (28) is deposited by a well-known vacuum evaporation method (see Fig. 3 (f) 11). By doing so, the Schottky barrier gate electrode (28) can be selectively formed in the trench (27) or a trench gate structure can be obtained.

(See Figure 3 (gJ)) However, in this method, the silicon nitride thin film (25) with a very small thickness is etched through the fine openings in the resist layer (26), so the side etching amount becomes large. There were problems such as cases where the side etching range was deviated from the appropriate width and reproducibility deteriorated.

This invention was made in order to solve the above-mentioned problems, and it is possible to arbitrarily adjust the width of the recess weave on which the gate electrode is deposited to a desired size of 1 liter,
The purpose is to improve DC and RF performance.

Means for Solving Problem E After forming a resist layer that has an opening in a part of the covering layer and covering the other part, the covering layer is removed by side etching through the opening in the resist layer, and then the semiconductor layer is removed. After etching and forming a groove corresponding to the width of the coating layer, a gate electrode is formed on the inner surface of the groove.
f.

C Effect J In the method for manufacturing a field effect transistor according to the present invention, the gate recess width is controlled to a width corresponding to the width of the covering layer formed in advance, so that the gate recess width can be controlled arbitrarily by selecting the covering layer width. This allows for improved DC and RF performance.

[Example] Hereinafter, an example of the method of this invention will be described with reference to FIGS.
This will be explained in detail with reference to (1).

In the method of this example, first, a semi-gloss M Q&A 8 substrate (1
), by a well-known vapor phase epitaxial growth method or the like, an n-type GaAs semiconductor layer (2) t- which will become a channel layer is formed.
The GaAs semiconductor layer (2) is grown, and drain electrodes (3) and source electrodes (4) made of, for example, germanium are selectively deposited at predetermined intervals on the surface of the GaAs semiconductor layer (2) (see Figure 4PJ1 (a)). ), and a first coating layer (5), for example, a Si3N4 layer, is formed on these to a predetermined thickness by the well-known plasma CVD method (FIG. 1(b)).

Next, a first recess having a width corresponding to a desired gate recess is formed at a desired position on the Si3N4 layer (5) in the so-called channel region between the drain electrode (3) and the source electrode (4).
To form a resist layer (6) (Fig. 1(C)), use this first resist layer (6) as a mask to form a 5i3JJ4 layer (Fig. 1(C)).
After selectively etching 5), the first resist layer (
b)? By removing Si3N4 as a first covering layer <5) formed on the semiconductor layer (2) between the drain electrode (3) and the wax wax (4) with a width corresponding to the selective rise width. Obtain a layer pattern (Figure 1 (dJ)) Next, form a second resist layer (7) that has openings in a part of this first coating layer (5) pattern 5 and covers the rest. (Figure 1(e)).

Thereafter, using the second resist layer as a mask, part of the first coating layer (5) pattern is completely removed from the opening by etching (f), and then the second resist layer is etched. Using the layer as a mask, the semiconductor layer (
2) to a predetermined depth to form the first coating layer (5).
A one-sided adhesive region (8) corresponding to the pattern width is formed (see FIG. 1). Next, the well-known true '2I! A gate electrode (9) material such as aluminum is deposited by steaming or the like (Fig. 1 (h)).
, then by applying the 7 to 7 method, Schottky Paria Gate 1! A recessed gate structure is obtained in which the pole (9) is selectively formed in the recess @ region (8) (Fig. 1(i)
).

As described above, in the method of the embodiment of the present invention, the width of the gate recess region (8), which has a strong correlation with the E'ET performance, is
Since the pattern width of the first coating layer (5) can be controlled to any size by selecting the pattern width, improvements in DCP and RF performance can be achieved with good reproducibility.

In the above embodiment, Si3 is used as the first coating layer.
Although the case of using N4 has been described, the present invention is not limited to this, and the semiconductor layer forming the drain and source electrodes can be easily formed. Insulators or metals other than Si3N4 may be used that can be removed in a manner that does not corrode the second resist layer.

Further, although the case where aluminum is used as the gate electrode material has been described, other metals may be used.

Further, the material of the semiconductor layer is not limited to GaAs, but may be a 7e compound semiconductor, silicon, etc. In this case, appropriate materials for the drain, source, and gate electrodes are selected depending on the type of semiconductor material. Of course.

c Effects of the Invention J As detailed above, according to the method of the present invention, a coating layer having a shape corresponding to a desired gate recess width is provided at a predetermined position on the semiconductor layer between the source electrode and the drain electrode,
After forming a resist layer that has an opening in a part of the covering layer and covering the other part, the covering layer is removed by side etching through the opening in the resist layer, and then the semiconductor layer is etched, After forming a recessed region corresponding to the width of the covering layer, a gate electrode is formed on the inner surface of the recess, so that the gate recessed region can be controlled to a width corresponding to the width of the covering layer formed in advance. Therefore, the gate recess width can be arbitrarily controlled by selecting the covering layer width, and the DC and 1FtF characteristics can be improved.

[Brief explanation of drawings]

FIGS. 1(a) to (1) are cross-sectional views showing a method for manufacturing a GaAs MES F'ET having a recessed gate structure according to an embodiment of the method of the present invention, and FIGS. 2(a) to (d) and 3 Figures (a) to (a) show conventional recessed gate structure of GaA.
FIG. 2 is a step-by-step cross-sectional view showing a method for manufacturing an s MES FET. (1) is a semi-insulating GaAs substrate, (2) F
'in-type GaAs semicircular layer, (3) is the drain electrode, (
4) is the source electrode, (5) is the first coating layer, (6) is the first resist layer, (7) is the second resist layer, (8) is the beam suzaka, and (9) is the dirt electrode. be. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 3

Claims (3)

[Claims] (1) A first step in which a semiconductor layer is formed on one main surface of a semiconductor substrate.
a second step of forming a plurality of source electrodes and drain electrodes at predetermined intervals on one main surface of the semiconductor layer; a first coating on the source electrodes, drain electrodes, and semiconductor layer; A third step of forming a layer, a fourth step of forming a first resist layer of a predetermined width on the first coating layer between the source electrode and the drain electrode, and exposing the first resist layer using the first resist layer as a mask. a fifth step of forming a first covering layer pattern of a predetermined shape between the source electrode and the drain electrode by removing the first covering layer and then removing the first resist layer; a sixth step of forming a second resist pattern having openings of a predetermined width at desired positions of the covering layer pattern and covering the other parts; using the second resist pattern as a mask, forming the first covering layer pattern; a seventh step of removing the semiconductor layer; an eighth step of etching the exposed portion of the seventh step to form a recess in the semiconductor layer; and a ninth step of forming a Schottky barrier gate electrode on the inner surface of the recess of the semiconductor layer. A method for manufacturing a field effect transistor, comprising the steps of: (2) The method for manufacturing a field effect transistor according to claim 1, wherein the semiconductor layer is made of gallium arsenide. (3) A method for manufacturing a field effect transistor according to claim 1 or 2, characterized in that silicon nitride is used as the first covering layer.