JPH0415334U - - Google Patents

Info

Publication number
JPH0415334U
JPH0415334U JP5466490U JP5466490U JPH0415334U JP H0415334 U JPH0415334 U JP H0415334U JP 5466490 U JP5466490 U JP 5466490U JP 5466490 U JP5466490 U JP 5466490U JP H0415334 U JPH0415334 U JP H0415334U
Authority
JP
Japan
Prior art keywords
received
circuit
signals
generates
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5466490U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5466490U priority Critical patent/JPH0415334U/ja
Publication of JPH0415334U publication Critical patent/JPH0415334U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この考案によるシリアル通信回路の
一実施例を示すブロツク図、第2図AとBは、こ
の考案で対象とする通信系の送受信される信号の
構成図、第3図と第4図は、第2図AとBに示す
送受信される信号構成についてのタイミングチヤ
ートである。 1……m進カウンタ、2……RSフリツプフロ
ツプ、3……デコーダ、4……NAND回路、5
,7……AND回路、6……インバータ。
FIG. 1 is a block diagram showing an embodiment of a serial communication circuit according to this invention, FIGS. 2A and B are block diagrams of signals transmitted and received in the communication system targeted by this invention, and FIGS. FIG. 4 is a timing chart for the transmitted and received signal structure shown in FIGS. 2A and 2B. 1...m-ary counter, 2...RS flip-flop, 3...decoder, 4...NAND circuit, 5
, 7...AND circuit, 6...Inverter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] それぞれ異なる通信線でデータ信号とフレーム
同期信号が送受信される通信系からのデータを受
けて受信データ信号を生成出力する回路と、1本
の通信線によりデータ信号列中にフレーム同期信
号が含まれて送受信される通信系からのデータか
ら前記受信フレーム同期信号と受信データを生成
出力する回路とを備えて成ることを特徴とするシ
リアル通信回路。
There is a circuit that receives data from a communication system in which data signals and frame synchronization signals are transmitted and received over different communication lines, generates and outputs received data signals, and a circuit that generates and outputs received data signals by transmitting and receiving data signals and frame synchronization signals through a single communication line. 1. A serial communication circuit comprising: a circuit that generates and outputs the received frame synchronization signal and received data from data transmitted and received from a communication system.
JP5466490U 1990-05-28 1990-05-28 Pending JPH0415334U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5466490U JPH0415334U (en) 1990-05-28 1990-05-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5466490U JPH0415334U (en) 1990-05-28 1990-05-28

Publications (1)

Publication Number Publication Date
JPH0415334U true JPH0415334U (en) 1992-02-07

Family

ID=31576928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5466490U Pending JPH0415334U (en) 1990-05-28 1990-05-28

Country Status (1)

Country Link
JP (1) JPH0415334U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59194551A (en) * 1983-04-20 1984-11-05 Fujitsu Ltd Data communication system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59194551A (en) * 1983-04-20 1984-11-05 Fujitsu Ltd Data communication system

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