JPH03120129U - - Google Patents

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Publication number
JPH03120129U
JPH03120129U JP2877090U JP2877090U JPH03120129U JP H03120129 U JPH03120129 U JP H03120129U JP 2877090 U JP2877090 U JP 2877090U JP 2877090 U JP2877090 U JP 2877090U JP H03120129 U JPH03120129 U JP H03120129U
Authority
JP
Japan
Prior art keywords
line
plane
product term
programmable logic
delay circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2877090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2877090U priority Critical patent/JPH03120129U/ja
Publication of JPH03120129U publication Critical patent/JPH03120129U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示す図、第2図は上
記実施例に於ける信号の時間差調整による信号の
同期化手段を説明するためのタイムチヤート、第
3図は従来のプログラマブルロジツクアレイの構
成説明図である。 101……AND平面、102……OR平面、
103……入力線、104……積項線、105…
…出力線、106……デイレイ回路。
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining the signal synchronization means by adjusting the signal time difference in the above embodiment, and Fig. 3 is a diagram showing a conventional programmable logic. FIG. 2 is an explanatory diagram of the configuration of an array. 101...AND plane, 102...OR plane,
103...Input line, 104...Product term line, 105...
...output line, 106...delay circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アンド平面とオア平面を結ぶ線(積項線)上に
デイレイ回路を挿入し、他の積項線を通る信号と
同期をとることにより信号線長に影響されない出
力信号を得ることを特徴とするプログラマブルロ
ジツクアレイ。
A delay circuit is inserted on the line (product term line) connecting the AND plane and the OR plane, and by synchronizing with signals passing through other product term lines, an output signal that is not affected by the signal line length is obtained. Programmable logic array.
JP2877090U 1990-03-20 1990-03-20 Pending JPH03120129U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2877090U JPH03120129U (en) 1990-03-20 1990-03-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2877090U JPH03120129U (en) 1990-03-20 1990-03-20

Publications (1)

Publication Number Publication Date
JPH03120129U true JPH03120129U (en) 1991-12-10

Family

ID=31531559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2877090U Pending JPH03120129U (en) 1990-03-20 1990-03-20

Country Status (1)

Country Link
JP (1) JPH03120129U (en)

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