JPH04150414A - Digital pll system - Google Patents

Abstract

PURPOSE:To improve the jitter suppressing characteristic of this system by discriminating the presence/absence of the mission of a write clock during the period from the occurrence of a carrying or borrowing output from an up-down counter to the overflow of a memory and, when the omission exists, invalidating the carrying or borrowing output. CONSTITUTION:In a digital PLL circuit 1, a phase comparator 10 compares the phase of a write clock WCK with that of a readout clock RCK and a pulse insertion/removal circuit 40 inserts or removes a pulse into or from the output of an oscillator 30. When a carrying or borrowing output CA or BO occurs, the number of clocks from the position where the output CA or BO occurs to the overflow of a memory is found and, when the omitted bit of the write clock WCK is present in the counted number of clocks, the carrying or borrowing output CA or BO outputted from an up-down counter 29 is invalidated so as to improve the clock jitter characteristic.

Description

[Detailed Description of the Invention] [Summary] Regarding the digital PLL method when performing format conversion using memory, when carry output and carry down output occur, the carry output and carry down output are determined depending on the generation phase. Digital PL with high clock jitter suppression characteristics by performing invalidation control
In a digital PLL circuit, when a carry output or carry down output of an up/down counter occurs, the carry output or carry down output from the up/down counter is determined depending on the generation phase. A control unit is provided to perform control to disable the
When carry output or carry down output occurs, the control unit calculates the number of clocks from the generation position until memory overflow occurs, and if there is a write clock bit within the number of clocks, The configuration is such that the carry output and carry down output output from the up/down counter are invalidated, and the up/down counter is reset.

[Industrial application field]

The present invention relates to a digital PLL method when performing format conversion using memory.

PLL (phase locked loop) has been widely used in recent years because of its high frequency stability.

Furthermore, with the advancement of digital technology, a compact and inexpensive digital PLL system in which phase synchronization is performed by digital control has been realized, and has been adopted in various communication devices, measuring instruments, and the like.

In the analog PLL system, the output of the phase comparator is converted into a DC component through a low-frequency wave generator and an integrating circuit, and input to the voltage controlled oscillator to control the output frequency. The output is integrated, and slight fluctuations are absorbed and do not appear as changes in the control voltage.

On the other hand, in the digital PLL method, control is performed digitally, so when a phase change is detected and the phase change exceeds the threshold level, control is performed immediately. Even if the level returns to below the threshold level immediately, since the control is performed digitally, the control is performed frequently, and this is output as jitter.

In such a digital PLL system, a system with good clock jitter suppression characteristics is required.

[Conventional technology]

FIG. 3 shows a block diagram illustrating a conventional example.

The conventional IA shown in FIG. 3 is a digital PLL circuit, and includes a phase comparator lO that compares the phases of a write clock WCK for writing data to the memory and a read clock RCK for reading data from the memory, and the output of the phase comparator 10. , an up-down counter 20 that outputs a carry output CA and a carry-down output BO, an oscillator 30, and a pulse added to and removed from the output of the oscillator 30 using the carry output CA and the carry-down output BO of the up-down counter 20. It consists of a pulse insertion/extraction circuit 40 that performs this, and a frequency divider 50 that frequency divides the output of the pulse insertion/extraction circuit 40.

In the above configuration, the phases of the write clock WCK for writing data and the read clock RCK for reading data from the memory are compared by the phase comparator 10, the phase difference output is counted by the up/down counter 20, and the count is set at the threshold on the up side. When the level is exceeded, a carry output CA is output, and when the down side threshold level is exceeded, a carry output BO is output.

The pulse insertion/extraction circuit 40 has a carry output CA and a carry down output B.
O adds and removes pulses to the output of the oscillator 30, and the output is input to the frequency divider 50 for phase synchronization.

[Problem to be solved by the invention]

In the conventional example described above, the write clock W is generated after the up/down counter 20 outputs the carry output CA or the carry down output BO until the memory overflows.
If CK has a missing bit, unnecessary carry or carry-down will occur, resulting in poor clock jitter characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital PLL system with high clock jitter suppression characteristics by performing control to invalidate carry output and carry down output depending on the generation phase when carry output and carry down output occur. shall be.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 1 indicates a digital PLL circuit, and 10 in the figure is a phase comparator that compares the phases of the write clock WCK for writing data into the memory and the read clock RCK for reading data from the memory. 20 is an up/down counter that outputs a carry output CA and a carry down output BO from the output of the phase comparator IO, 30 is an oscillator, and 40 is an up/down counter that outputs the carry output CA and digit of the up/down counter 20. This is a pulse insertion/extraction circuit that adds and removes pulses from the output of the oscillator 30 using the lowered output BO, and 50 is a frequency divider that divides the frequency of the output of the pulse insertion/extraction circuit 40.

Further, 60 is a carry output CA and a carry down output BO of the up/down counter 20 provided in the digital PLL circuit 1.
When , a carry output CA and a carry output BO are output from the up/down counter 20 depending on the phase of the occurrence.
When a carry output CA or a carry output BO occurs, it calculates the number of clocks from the occurrence position until a memory overflow occurs, and then writes the write clock within that number of clocks. W
When a bit exists in CK, carry output CA and carry down output B are output from the up/down counter 20.
This problem is solved by disabling O and resetting the up/down counter 20.

[For production]

In the digital PLL circuit 1, a phase comparator 10 compares the phases of a write clock WCK and a read clock RCK, and a pulse insertion/extraction circuit 40
Then, pulses are inserted and deleted in the output of the oscillator 30.

Since the control of insertion and deletion of pulses is performed digitally by controlling the up-down counter 20, pulses are inserted and removed even when the phase difference slightly exceeds the threshold level, which worsens clock jitter characteristics. There may be cases where

Therefore, when a carry output CA or a carry output BO occurs, calculate the number of clocks from that position until a memory overflow occurs, and if there is a bit of the write clock WCK within that number of clocks, then By invalidating the carry output CA and the carry down output BO output from the up/down counter 20, it is possible to improve the clock jitter characteristics.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a diagram illustrating an operation time chart of the present invention.

The operation will be explained using the time chart shown in FIG.

Here, the clock is changed for format conversion, data is written using a clock whose frequency is divided by 4, and data is read using a clock whose frequency is divided by 4.

■ Original write clock WCK.

■ It is write data. Although the data is input continuously, only 8 bits A to H are shown here.

■～■ Data A-H written using a clock divided by 4
It is.

■ Write clock WCK whose frequency is divided by 4.

■ Read clock RCK whose frequency is divided by 4.

Assume that there is a phase difference of Φ between the write clock WCK whose frequency is divided by 4 and the read clock RCK whose frequency is divided by 4, and a carry output CA (or a carry output BO) is outputted.

Since the period of the write clock WCK divided by 4 is a predetermined value, it is possible to find the number N of write clocks WCK until the memory overflows from the period τ of the write clock WCK and the phase difference Φ. be.

Furthermore, in this embodiment, since format conversion is performed using memory, the position where the bit is generated is also specified in the original write clock WCK.

Therefore, it is possible to determine whether or not a bit is generated by cutting out the original write clock WCK within the number N of clocks until the memory overflows.
If there is a bit, the clock jitter characteristics can be improved by not controlling the digital PLL.

〔Effect of the invention〕

According to the present invention as described above, it is determined whether there is a gap in the write clock after the carry output or carry down output from the up/down counter occurs until the memory overflows. , it is possible to provide a digital PLL system with excellent jitter suppression characteristics by disabling carry output and carry output when there is a missing tooth.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the present invention in detail, FIG. 2 is a diagram illustrating an operation time chart of the present invention, and FIG. 3 is a block diagram illustrating a conventional example. In the figure, 10 is a phase comparator, 20 is an up/down counter, 30 is an oscillator, 40 is a pulse insertion/extraction circuit, 50 is a frequency divider, and 60 is a control unit. Diagram for explaining the operation time chart of the present invention. Diagram for explaining the conventional example.

Claims (1)

[Claims] Write clock (WCK) for writing data to memory
and a read clock (RC) that reads data from memory.
A phase comparator (10) that compares the phase of the phase comparator (10), and a carry output (CA
) and a carry output (BO), an oscillator (30), and a carry output (CA) of the up/down counter (20).
) and a carry-down output (BO) to add and remove pulses from the output of the oscillator (30); and a frequency divider (40) to divide the output of the pulse insertion/extraction circuit (40).
50), the carry output (CA
), a control unit that performs control to invalidate the carry output (CA) and the carry down output (BO) output from the up/down counter (20) according to the generation phase when the carry output (BO) is generated. (60) is provided, and when a carry output (CA) or a carry down output (BO) occurs, the control unit (60) calculates the number of clocks from the generation position until a memory overflow occurs, and calculates the number of clocks from the generation position until the memory overflow occurs. When there is a missing bit in the write clock (WCK), the carry output (CA) and carry output (BO) output from the up/down counter (20) are invalidated, and the up/down counter (20) ) is a digital PLL method that is characterized by resetting.