JPH0414857A - Lead terminal structure for electronic component - Google Patents

Lead terminal structure for electronic component

Info

Publication number
JPH0414857A
JPH0414857A JP11784590A JP11784590A JPH0414857A JP H0414857 A JPH0414857 A JP H0414857A JP 11784590 A JP11784590 A JP 11784590A JP 11784590 A JP11784590 A JP 11784590A JP H0414857 A JPH0414857 A JP H0414857A
Authority
JP
Japan
Prior art keywords
lead terminal
electronic component
terminal
lead
soldered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11784590A
Other languages
Japanese (ja)
Inventor
Mitsuru Sato
満 佐藤
Shuichi Tani
周一 谷
Saneyasu Hirota
弘田 実保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11784590A priority Critical patent/JPH0414857A/en
Publication of JPH0414857A publication Critical patent/JPH0414857A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To alleviate a thermal stress due to the difference of linear expansion coefficient and to reduce a fatigue damage of a soldered part of lead terminal of an electronic component by so disposing the lead terminal of the component as to protrude obliquely to the side of the component. CONSTITUTION:Lead terminals 1 are so disposed as to protrude obliquely to the side of an electronic component, and electrode bonding parts of the ends are soldered to electrodes. Accordingly, when a force is applied to the terminal 1 by the difference of linear expansion coefficients, a semiconductor package 2 is slightly rotated in a plane by its reaction, thereby alleviating a strain to be applied to the terminal 1. That it, only a vertical force is applied to a conventional lead terminal, but a vertical force is alleviated by an oblique deformation to reduce the fatigue damage of the soldered part.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、電子部品、特にクワッド・フラット・パッ
ケージ形半導体部品のリード端子構造の改良に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in the lead terminal structure of electronic components, particularly quad flat package type semiconductor components.

〔従来の技術〕[Conventional technology]

第2図(a)はr MI丁51JBISHI SEMI
CONDIJCTOR1988P3−100 Jに示さ
れた、クワッドフラットパッケージ(QFP)型の電子
部品における従来のリート端子構造を平面的に示した図
である。同図(b)は同電子部品のリード端子構造を示
した図である。図において、(1)はリード端子、(2
)は半導体パッケージ、(3)はリード端子(1)の半
田付けによって半導体パッケージ(2)を実装する基板
である。
Figure 2 (a) is r MI Ding 51JBISHI SEMI
FIG. 2 is a plan view showing a conventional lead terminal structure in a quad flat package (QFP) type electronic component shown in CONDIJCTOR1988P3-100J. FIG. 5B is a diagram showing the lead terminal structure of the electronic component. In the figure, (1) is a lead terminal, (2
) is a semiconductor package, and (3) is a board on which the semiconductor package (2) is mounted by soldering the lead terminals (1).

上記半導体パッケージ(2)の各リード端子(1)はパ
ッケージ本体の各面より垂直に突き出し、リート端子中
途より基板に対して垂直方向に折曲し、先端の電極接合
部が基板上のパターン電極に接し、半田接合させる。そ
して、各リード端子(1)は基板(3)の水平面内では
パッケージ本体側面に対して常に垂直である。
Each lead terminal (1) of the semiconductor package (2) protrudes perpendicularly from each surface of the package body, and is bent in the direction perpendicular to the substrate from the middle of the lead terminal, so that the electrode joint at the tip is connected to the pattern on the substrate. and solder them together. Each lead terminal (1) is always perpendicular to the side surface of the package body within the horizontal plane of the substrate (3).

(発明が解決しようとする課題) 従来の電子部品のリート端子構造は、以上のよ構成され
ているので、基板と半導体パッケージに温度変化が生じ
ると、線膨張係数の差により、基板に対して垂直方向に
立設したリード端子には垂直方向のみに伸縮変化が発生
してリード端子の半田接合部に繰り返しの負荷が加わり
、半導体装置ケージ本体或は基板の熱疲労破壊の原因と
なるなどの問題点があった。
(Problem to be Solved by the Invention) Since the conventional REIT terminal structure of electronic components is configured as described above, when a temperature change occurs between the substrate and the semiconductor package, the difference in linear expansion coefficient causes the substrate to Lead terminals installed vertically can expand and contract only in the vertical direction, which applies repeated loads to the solder joints of the lead terminals, which can cause thermal fatigue damage to the semiconductor device cage body or substrate. There was a problem.

この発明は上記のような問題点を解消するためになされ
たもので、リード端子の半田接合部にかかる負荷を少な
くすることを目的とする。
This invention was made to solve the above-mentioned problems, and its purpose is to reduce the load applied to the solder joints of lead terminals.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る電子部品のリード端子構造は、回路基板
の部品実装面にプリントされた各電極に、それぞれリー
ド端子を半田接合する面実装型の電子部品の各リード端
子を、電子部品の側面に対して斜め方向に突出配置し、
先端の電極接合部分を各電極に半田接合するよう各リー
ド端子を成形したものである。
In the lead terminal structure of an electronic component according to the present invention, each lead terminal of a surface-mounted electronic component is soldered to each electrode printed on the component mounting surface of a circuit board. Protruding diagonally from the opposite direction,
Each lead terminal is molded so that the electrode joining portion at the tip is soldered to each electrode.

〔作用〕[Effect]

この発明におけるリード端子は、線膨張係数の違いによ
る熱変形を、パッケージに対して垂直方向から斜め方向
へ移行させ、パッケージ全体を若干回転させるようにし
てリード半田接合端子への負荷を軽減する。
In the lead terminal of the present invention, thermal deformation due to the difference in coefficient of linear expansion is shifted from a direction perpendicular to the package to an oblique direction, and the entire package is slightly rotated, thereby reducing the load on the lead solder joint terminal.

〔実施例] 以下、この発明の一実施例を図について説明する。第1
図(a)は本実施例における半導体パッケージの上面図
、同図(b)は同パッケージの側面図である。第1図(
a) において、(1)はパッケージ端より斜め方向に
突出したリード端子、(2)は半導体パッケージ、(3
)はパッケージを半田付けする基板である。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
Figure (a) is a top view of the semiconductor package in this example, and Figure (b) is a side view of the same package. Figure 1 (
In a), (1) is a lead terminal protruding diagonally from the edge of the package, (2) is a semiconductor package, and (3) is a lead terminal protruding diagonally from the edge of the package.
) is the board to which the package is soldered.

次に、上記斜め方向に突出させたリート端子の熱歪み軽
減に対する効力を説明する。
Next, the effect of the above-described diagonally protruding REIT terminal on reducing thermal strain will be explained.

線膨張係数の差により、リード端子(1)に力が加わる
と、その反作用により、半導体パッケージ(2)は面内
で僅かに回転し、それによりリード端子(1)に加わる
歪みを軽減する。即ち、従来ではリード端子に垂直な力
のみが加わっていたものが、斜め方向の変形が生じるこ
とによフて垂直方向の力が緩和され、半田付部分の疲労
破壊が少なくなる。
When force is applied to the lead terminal (1) due to the difference in coefficient of linear expansion, the semiconductor package (2) slightly rotates within the plane due to the reaction, thereby reducing the strain applied to the lead terminal (1). That is, conventionally, only a vertical force was applied to the lead terminal, but due to the diagonal deformation, the vertical force is alleviated, and fatigue failure of the soldered portion is reduced.

なお、上記実施例では、リード端子(2)を直線形状と
したものを示したが、リードの形状は曲線形状であって
もよく、リード端子の付根の位置と半田付けする部分の
位置かずれていればリードの形状には依存しない。また
上記実施例では、QFP(Quad Flat Pac
kage)の場合を示したが、DIP(Dual In
1ine Package)や他の形状であっても良く
、上記実施例と同様の効果を奏する。
In the above embodiment, the lead terminal (2) has a linear shape, but the shape of the lead may be a curved shape, and the position of the base of the lead terminal and the part to be soldered may be misaligned. If it is, it does not depend on the shape of the lead. Further, in the above embodiment, QFP (Quad Flat Pac
Although the case of DIP (Dual In
1ine Package) or other shapes may be used, and the same effects as in the above embodiments can be achieved.

(発明の効果) 以上のように、この発明によれば電子部品のり−上端子
を電子部品の側面に対して斜め方向に突出させて配置し
たので、線膨張係数の違いによる熱応力を緩和でき、リ
ード端子の半田接合部分の疲労破壊を少なくすることが
できる。
(Effects of the Invention) As described above, according to the present invention, the upper terminal of the electronic component glue is arranged so as to protrude diagonally from the side surface of the electronic component, so that thermal stress due to the difference in linear expansion coefficient can be alleviated. , it is possible to reduce fatigue failure of the solder joint portion of the lead terminal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)はこの発明の一実施例によるり−上端子を
備えた半導体パッケージの上面図、第1図(b)は同側
面図である。第2図(a)は従来の半導体パッケージの
上面図、′fS2図(b)は同側面図である。 (1)はリード端子、(2)は半導体パッケージ、(3
)は基板である。 なお、図中、同一符号は同一、または相当部分を示す。
FIG. 1(a) is a top view of a semiconductor package equipped with an upper terminal according to an embodiment of the present invention, and FIG. 1(b) is a side view of the same. FIG. 2(a) is a top view of a conventional semiconductor package, and FIG. 2(b) is a side view of the same. (1) is a lead terminal, (2) is a semiconductor package, (3)
) is the substrate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims]  回路基板の部品実装面にプリントされた各電極に、そ
れぞれリード端子を半田接合する面実装型の電子部品の
リーダ端子において、各リード端子を電子部品の側面に
対して斜め方向に突出配置し、先端の電極接合部分を各
電極に半田接合するよう各リード端子を成形したことを
特徴とする電子部品のリード端子構造。
In the leader terminal of a surface-mount electronic component in which lead terminals are soldered to each electrode printed on the component mounting surface of the circuit board, each lead terminal is arranged to protrude diagonally from the side surface of the electronic component, A lead terminal structure for an electronic component, characterized in that each lead terminal is molded so that the electrode joint portion at the tip is soldered to each electrode.
JP11784590A 1990-05-08 1990-05-08 Lead terminal structure for electronic component Pending JPH0414857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11784590A JPH0414857A (en) 1990-05-08 1990-05-08 Lead terminal structure for electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11784590A JPH0414857A (en) 1990-05-08 1990-05-08 Lead terminal structure for electronic component

Publications (1)

Publication Number Publication Date
JPH0414857A true JPH0414857A (en) 1992-01-20

Family

ID=14721697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11784590A Pending JPH0414857A (en) 1990-05-08 1990-05-08 Lead terminal structure for electronic component

Country Status (1)

Country Link
JP (1) JPH0414857A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018110143A (en) * 2016-12-28 2018-07-12 三菱電機株式会社 Semiconductor device, power converter, lead frame, and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018110143A (en) * 2016-12-28 2018-07-12 三菱電機株式会社 Semiconductor device, power converter, lead frame, and manufacturing method of semiconductor device

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