JPH0758247A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH0758247A
JPH0758247A JP19972893A JP19972893A JPH0758247A JP H0758247 A JPH0758247 A JP H0758247A JP 19972893 A JP19972893 A JP 19972893A JP 19972893 A JP19972893 A JP 19972893A JP H0758247 A JPH0758247 A JP H0758247A
Authority
JP
Japan
Prior art keywords
leads
package body
package
semiconductor package
corners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19972893A
Other languages
Japanese (ja)
Inventor
Kenji Kaji
健 二 梶
Rikio Okabe
部 力 男 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19972893A priority Critical patent/JPH0758247A/en
Publication of JPH0758247A publication Critical patent/JPH0758247A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To restrain an excessive stress from being applied onto leads even if a board is warped or an external force is applied to a package. CONSTITUTION:A nearly L-shaped leg 6 is provided to each of the four corners of a package main body 2 of a QFP 1 coming into contact with a printed board 4. Leads 3 are soldered to pads 5 making the undersides of the legs 6 bear against the printed board 4. Even if the printed board 4 is warped or the package main body 2 is pressed down, the package main body 2 and the printed board 4 are not lessened in relative distance between them near the corners of the package main body 2 because the legs 6 bear against the printed board 4. Therefore, the leads 3 are almost set free from a tortional stress or the like, so that the leads 3 are restrained from separating off from the pads 5, the soldered joints of the leads 3 are prevented from deteriorating in strength, and the leads 3 are hardly broken.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体パッケージに係
り、特に基板が反ったりパッケージ本体が押下げられた
場合等における、基板のパッドからのリードの剥がれや
リードの折損等を防止したものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and, more particularly, to a semiconductor package which prevents peeling of a lead from a pad of a substrate and breakage of the lead when the substrate is warped or the package body is pushed down.

【０００２】[0002]

【従来の技術】近年、半導体の実装には、旧来のＳＯＰ
（Small Outline Package ）の他、超多ピンに対応でき
るＱＦＰ（Quad Flat Package ）やＰＧＡ（Pin Grid A
rray）等の半導体パッケージが広範に用いられている。2. Description of the Related Art In recent years, conventional SOP has been used for mounting semiconductors.
In addition to (Small Outline Package), QFP (Quad Flat Package) and PGA (Pin Grid A) that can support a large number of pins
Semiconductor packages such as rray) are widely used.

【０００３】図１１に示したように、ＱＦＰやＰＧＡ等
（以下、ＱＦＰで代表させる）１は、セラミックや合成
樹脂等からなるパッケージ本体２の四辺に薄い銅合金板
等からなる多数本のリード（ピン）３を配設したもので
ある。ＱＦＰ１の実装においては、パッケージ本体２を
プリント基板４上に載置してリード３をパッド５に当接
させ、赤外線やレーザ光線を用いたリフロー法等により
半田接合を行う。実装後には、パッケージ本体２はプリ
ント基板４の上方に浮いた状態となり、リード３により
支えられる。As shown in FIG. 11, a QFP, PGA or the like (hereinafter represented by QFP) 1 has a large number of leads made of thin copper alloy plates or the like on four sides of a package body 2 made of ceramic, synthetic resin or the like. (Pin) 3 is provided. In mounting the QFP 1, the package body 2 is placed on the printed circuit board 4, the leads 3 are brought into contact with the pads 5, and soldering is performed by a reflow method using infrared rays or a laser beam. After mounting, the package body 2 floats above the printed circuit board 4 and is supported by the leads 3.

【０００４】[0004]

【発明が解決しようとする課題】周知のように、パッケ
ージ本体２の四辺に多数本のリード３を配設したＱＦＰ
１では、リード３のピッチ間隔は極めて短い。したがっ
て、リード３もこれに応じて幅の狭いものを用いざるを
得ず、半田接合の面積も小さくなる。一方、熱や外力等
により、プリント基板３に図１２に示したような反りや
捩じれが生じた場合、リード３には大きなストレスが作
用する。特に、パッケージ本体２の四隅付近（図１２中
にａで示す）では、パッケージ本体２とプリント基板４
との相対角度が大きくなると共にその距離も小さくな
り、リード３には捩じり応力が強く作用する。その結
果、図１３に示したように、リード３がプリント基板４
のパッド５から剥がれたり、半田接合部の強度が低下す
る虞があった。また、図１４に示したように、パッケー
ジ本体２に押下力が加わって基板４の表面に当接した場
合、図１５に示したように、リード３に過大な応力が掛
り折損する虞があった。As is well known, a QFP in which a large number of leads 3 are arranged on four sides of a package body 2 is known.
In No. 1, the pitch interval of the leads 3 is extremely short. Therefore, the lead 3 is inevitably used with a narrow width accordingly, and the area of the solder joint is also reduced. On the other hand, when the printed circuit board 3 is warped or twisted as shown in FIG. 12 due to heat or external force, a large stress acts on the leads 3. Particularly, in the vicinity of the four corners of the package body 2 (indicated by a in FIG. 12), the package body 2 and the printed circuit board 4 are
As the relative angle between and increases, the distance also decreases, and the torsional stress acts strongly on the lead 3. As a result, as shown in FIG.
There is a risk that it may be peeled off from the pad 5 or the strength of the solder joint may be reduced. In addition, as shown in FIG. 14, when a pressing force is applied to the package body 2 and the package body 2 comes into contact with the surface of the substrate 4, as shown in FIG. 15, the lead 3 may be excessively stressed and may be broken. It was

【０００５】そこで、本発明は、上記従来技術が有する
問題点を解消し、基板が反ったりパッケージ本体に押下
力が加わった場合にも、リードに過大なストレスが掛か
らないようにした半導体パッケージを提供することを目
的とする。Therefore, the present invention provides a semiconductor package which solves the above-mentioned problems of the prior art and prevents the leads from being excessively stressed even when the substrate warps or the package body is pressed down. The purpose is to provide.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明の第１の半導体パッケージは、パッケージ本
体の周囲に基板のパッドに接続される多数本のリードを
配設してなる半導体パッケージであって、前記パッケー
ジ本体の基板側の面の四隅に基板に当接する脚部を突設
したことを特徴とする。In order to achieve the above object, the first semiconductor package of the present invention is a semiconductor in which a large number of leads connected to pads of a substrate are arranged around the package body. The package is characterized in that leg portions that come into contact with the substrate are provided at four corners of a surface of the package body on the substrate side.

【０００７】また、本発明の第２の半導体パッケージ
は、パッケージ本体の周囲に基板のパッドに接続される
多数本のリードを配設してなる半導体パッケージであっ
て、前記パッケージ本体の基板側の面の四隅に基板と所
定の間隙をもって対峙する突起を形成したことを特徴と
する。The second semiconductor package of the present invention is a semiconductor package in which a large number of leads connected to the pads of the substrate are arranged around the package body, and the semiconductor package on the substrate side of the package body is provided. It is characterized in that projections facing the substrate are formed at four corners of the surface with a predetermined gap.

【０００８】更に、本発明の第３の半導体パッケージ
は、パッケージ本体の周囲に基板のパッドに接続される
多数本のリードを配設してなる半導体パッケージであっ
て、前記パッケージ本体の四隅に前記パッドに接続され
る補強用リードを形成したことを特徴とする。Furthermore, a third semiconductor package of the present invention is a semiconductor package in which a large number of leads connected to pads of a substrate are arranged around the package body, and the four leads are provided at four corners of the package body. It is characterized in that a reinforcing lead connected to the pad is formed.

【０００９】[0009]

【作用】本発明の半導体パッケージによれば、基板に反
りや捩じれが生じた場合、パッケージ本体の四隅に形成
された突起や補強用リードにより、基板とパッケージ本
体との相対距離の変動が小さくなる。その結果、四隅付
近のリードに作用する捩じり応力が小さくなり、リード
のパッドからの剥がれや半田接合部の強度低下が防止さ
れる。また、パッケージ本体に下向に押下力が加わった
場合にも、突起や補強用リードによりパッケージ本体の
移動が防止あるいは軽減される。According to the semiconductor package of the present invention, when the substrate is warped or twisted, the projections and the reinforcing leads formed at the four corners of the package body reduce variations in the relative distance between the substrate and the package body. . As a result, the torsional stress acting on the leads near the four corners is reduced, and peeling of the leads from the pads and reduction in strength of the solder joints are prevented. Further, even when a downward pressing force is applied to the package body, the movement of the package body is prevented or reduced by the protrusions and the reinforcing leads.

【００１０】[0010]

【実施例】以下、本発明による半導体パッケージの実施
例について、添付の図面を参照して説明する。尚、実施
例の説明にあたっては前述した従来装置と同一の部材に
は同一の符号を付し、重複する説明を省略する。図１お
よび図２には、第１実施例のＱＦＰを示してある。これ
らの図に示したように、本実施例のＱＦＰ１では、パッ
ケージ本体２のプリント基板４側の四隅に、それぞれ略
Ｌ字形状の脚部６が形成されている。そして、パッド５
へのリード３の半田接合は、これら脚部６の底面がプリ
ント基板４に当接した状態で行われる。Embodiments of the semiconductor package according to the present invention will be described below with reference to the accompanying drawings. In the description of the embodiments, the same members as those of the conventional device described above are designated by the same reference numerals, and duplicated description will be omitted. 1 and 2 show the QFP of the first embodiment. As shown in these figures, in the QFP 1 of this embodiment, substantially L-shaped legs 6 are formed at the four corners of the package body 2 on the printed circuit board 4 side. And pad 5
The soldering of the lead 3 to the lead 3 is performed with the bottom surfaces of the leg portions 6 in contact with the printed circuit board 4.

【００１１】本実施例においては、プリント基板４が反
っても、脚部６がプリント基板４に当接しているため、
図３に示したように、四隅付近におけるパッケージ本体
２とプリント基板４との相対距離は小さくならず、逆に
若干大きくなる。したがって、リード３には捩じれ応力
は殆ど作用せず、リード３がプリント基板４のパッド５
から剥がれたり、半田接合部の強度が低下することがな
くなった。また、パッケージ本体２に押下げる力が加わ
っても、脚部６が当接しているため、プリント基板４と
の相対距離は変わらず、リード３の折損等は生じない。
尚、本実施例では脚部６はプリント基板４に単に当接し
ているだけであるが、接着剤等により固着させるように
してもよい。In this embodiment, even if the printed circuit board 4 warps, the leg portions 6 are in contact with the printed circuit board 4,
As shown in FIG. 3, the relative distances between the package body 2 and the printed circuit board 4 near the four corners are not small, but are rather large. Therefore, the torsional stress hardly acts on the lead 3, and the lead 3 is not attached to the pad 5 of the printed circuit board 4.
It did not peel off or the strength of the solder joint did not decrease. Further, even if a pressing force is applied to the package body 2, since the legs 6 are in contact with each other, the relative distance to the printed circuit board 4 does not change, and the leads 3 are not broken.
In this embodiment, the leg 6 is merely in contact with the printed circuit board 4, but it may be fixed by an adhesive or the like.

【００１２】図４および図５には、第２実施例のＱＦＰ
を示してある。これらの図に示したように、本実施例の
ＱＦＰ１では、パッケージ本体２のプリント基板４側の
四隅に、それぞれ矩形の突起７が形成されている。そし
て、のパッド５へのリード３の半田接合は、これら突起
７の底面がプリント基板４から若干浮いた状態で行われ
る。FIGS. 4 and 5 show the QFP of the second embodiment.
Is shown. As shown in these figures, in the QFP 1 of this embodiment, rectangular protrusions 7 are formed at the four corners of the package body 2 on the printed circuit board 4 side. Then, the solder bonding of the lead 3 to the pad 5 is performed with the bottom surfaces of the protrusions 7 slightly floating from the printed circuit board 4.

【００１３】本実施例においてプリント基板４が反る
と、所定の反り量で突起７がプリント基板４に当接す
る。そのため、図６に示したように、四隅付近における
パッケージ本体２とプリント基板４との相対距離はあま
り小さくならない。したがって、第１実施例と同様にリ
ード３には捩じれ応力は殆ど作用せず、リード３がプリ
ント基板４のパッド５から剥がれたり、半田接合部の強
度が低下することがなくなった。また、パッケージ本体
２に押下げる力が加わっても、図７に示したように、突
起７がプリント基板４の表面に当接した時点でパッケー
ジ本体２は下降しなくなり、リード３の折損が防止され
る。In this embodiment, when the printed circuit board 4 is warped, the projection 7 comes into contact with the printed circuit board 4 with a predetermined amount of warpage. Therefore, as shown in FIG. 6, the relative distances between the package body 2 and the printed board 4 near the four corners do not become so small. Therefore, similar to the first embodiment, the torsional stress hardly acts on the lead 3, and the lead 3 is not peeled off from the pad 5 of the printed board 4 and the strength of the solder joint is not reduced. Further, even if a pressing force is applied to the package body 2, as shown in FIG. 7, the package body 2 does not descend when the protrusion 7 comes into contact with the surface of the printed circuit board 4, preventing breakage of the leads 3. To be done.

【００１４】図８および図９には第３実施例のＱＦＰを
示してある。これらの図に示したように、本実施例のＱ
ＦＰ１では、パッケージ本体２のプリント基板４側の四
隅にそれぞれ補強用リード８が形成されている。補強用
リード８は、他のリード３より断面が数倍大きく、強度
および剛性が非常に高くなっている。そして、パッド５
へのリード３の半田接合と同時に、これら補強用リード
８もグランド端子９に半田接合される。FIGS. 8 and 9 show a QFP of the third embodiment. As shown in these figures, the Q
In the FP1, reinforcing leads 8 are formed at the four corners of the package body 2 on the printed circuit board 4 side. The reinforcing lead 8 has a cross section several times larger than the other leads 3 and has extremely high strength and rigidity. And pad 5
At the same time that the leads 3 are soldered to the ground leads 9, the reinforcing leads 8 are also soldered to the ground terminals 9.

【００１５】本実施例においては、プリント基板４が反
った場合、補強用リード８は、その強度および剛性が他
のリード３に比べて遥かに高いため、変形量が極めて少
ない。そのため、図１０に示したように、四隅付近にお
けるパッケージ本体２とプリント基板４との相対距離は
あまり小さくならない。したがって、上記実施例と同様
にリード３には捩じれ応力は殆ど作用せず、リード３が
プリント基板４のパッド５から剥がれたり、半田接合部
の強度が低下することがなくなった。また、パッケージ
本体２に押下力が加わっても、補強用リード８がその押
下力に抗するため、第２実施例と同様にパッケージ本体
２の下降量が少なくなり、リード３の折損が防止され
る。更に、補強用リード８がグランド端子９に接合され
ることにより、グランドパターンの強化も可能となっ
た。In this embodiment, when the printed circuit board 4 is warped, the reinforcing lead 8 has much higher strength and rigidity than the other leads 3, so that the amount of deformation is extremely small. Therefore, as shown in FIG. 10, the relative distances between the package body 2 and the printed circuit board 4 near the four corners do not become so small. Therefore, as in the above-described embodiment, the torsional stress hardly acts on the lead 3, the lead 3 is not peeled off from the pad 5 of the printed board 4, and the strength of the solder joint is not reduced. Further, even if the pressing force is applied to the package body 2, the reinforcing lead 8 resists the pressing force, so that the amount of lowering of the package body 2 is reduced and the lead 3 is prevented from being broken as in the second embodiment. It Further, by joining the reinforcing lead 8 to the ground terminal 9, it is possible to strengthen the ground pattern.

【００１６】以上で具体的実施例の説明を終えるが、本
発明の態様はこれらの実施例に限られるものではなく、
例えばＰＧＡやＳＯＰ等の半導体パッケージに本発明を
適用してもよい。また、第２実施例ではパッケージ本体
の四隅に矩形の突起を形成したが、パッケージ本体の大
きさやリードの長さ等に応じ、中央よりに形成してもよ
いし、突起の形状を円形等にしてもよい。Although the description of the specific embodiments is finished above, the aspect of the present invention is not limited to these embodiments,
For example, the present invention may be applied to a semiconductor package such as PGA or SOP. In addition, although the rectangular protrusions are formed at the four corners of the package body in the second embodiment, they may be formed from the center depending on the size of the package body, the length of the leads, etc. May be.

【００１７】[0017]

【発明の効果】以上の説明から明らかなように、本発明
の半導体パッケージによれば、パッケージ本体の四隅に
基板に当接する突起やグランド端子に接合される補強用
リードを形成し、基板の反りやパッケージ本体が押下げ
られた際の基板とパッケージ本体との相対距離の変動が
小さくなるようにしたため、四隅付近のリードに作用す
る捩じり応力が小さくなり、リードのパッドからの剥が
れ、半田接合部の強度低下およびリードの折損が防止さ
れる。また、補強用リードをグランド端子に接合したも
のにあっては、グランドパターンの強化も実現される。As is apparent from the above description, according to the semiconductor package of the present invention, the protrusions contacting the substrate and the reinforcing leads joined to the ground terminals are formed at the four corners of the package body, and the warp of the substrate is caused. Since the variation in the relative distance between the board and the package body when the package body or the package body is pressed down is reduced, the torsional stress that acts on the leads near the four corners is reduced, and the lead is removed from the pad and soldered. It is possible to prevent the strength of the joint from being lowered and the lead to be broken. Further, in the case where the reinforcing lead is joined to the ground terminal, the ground pattern can be strengthened.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係る半導体パッケージの第１実施例を
示した斜視図。FIG. 1 is a perspective view showing a first embodiment of a semiconductor package according to the present invention.

【図２】同側面図。FIG. 2 is a side view of the same.

【図３】プリント基板が反った際の、第１実施例の状態
を示した要部拡大図。FIG. 3 is an enlarged view of an essential part showing the state of the first embodiment when the printed circuit board is warped.

【図４】本発明に係る半導体パッケージの第２実施例を
示した斜視図。FIG. 4 is a perspective view showing a second embodiment of the semiconductor package according to the present invention.

【図５】同側面図。FIG. 5 is a side view of the same.

【図６】プリント基板が反った際の、第２実施例の状態
を示した要部拡大図。FIG. 6 is an enlarged view of an essential part showing the state of the second embodiment when the printed circuit board is warped.

【図７】パッケージ本体が押下げられた際の、第２実施
例の状態を示した要部拡大図。FIG. 7 is an enlarged view of an essential part showing the state of the second embodiment when the package body is pushed down.

【図８】本発明に係る半導体パッケージの第３実施例を
示した斜視図。FIG. 8 is a perspective view showing a third embodiment of the semiconductor package according to the present invention.

【図９】同側面図。FIG. 9 is a side view of the same.

【図１０】プリント基板が反った際の、第２実施例の状
態を示した要部拡大図。FIG. 10 is an enlarged view of an essential part showing the state of the second embodiment when the printed circuit board is warped.

【図１１】従来の半導体パッケージの一例を示した斜視
図。FIG. 11 is a perspective view showing an example of a conventional semiconductor package.

【図１２】プリント基板が反った際の、従来の半導体パ
ッケージの状態を示した側面図。FIG. 12 is a side view showing a state of a conventional semiconductor package when a printed circuit board is warped.

【図１３】同拡大側面図。FIG. 13 is an enlarged side view of the same.

【図１４】パッケージ本体が押下げられた際の、従来の
半導体パッケージの状態を示した側面図。FIG. 14 is a side view showing a state of a conventional semiconductor package when the package body is pushed down.

【図１５】同拡大側面図。FIG. 15 is an enlarged side view of the same.

【符号の説明】[Explanation of symbols]

１ ＱＦＰ（半導体パッケージ） ２ パッケージ本体 ３ リード ４ プリント基板 ５ パッド ６ 脚部 ７ 突起 ８ 補強用リード ９ グランド端子 1 QFP (semiconductor package) 2 package body 3 lead 4 printed circuit board 5 pad 6 leg 7 protrusion 8 reinforcement lead 9 ground terminal

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】パッケージ本体の周囲に基板のパッドに接
続される多数本のリードを配設してなる半導体パッケー
ジであって、前記パッケージ本体の基板側の面の四隅に
基板に当接する脚部を突設したことを特徴とする半導体
パッケージ。1. A semiconductor package in which a large number of leads connected to pads of a substrate are arranged around a package body, and leg portions contacting the substrate at four corners of the surface of the package body on the substrate side. A semiconductor package, which is characterized by having a protrusion. 【請求項２】パッケージ本体の周囲に基板のパッドに接
続される多数本のリードを配設してなる半導体パッケー
ジであって、前記パッケージ本体の基板側の面の四隅に
基板と所定の間隙をもって対峙する突起を形成したこと
を特徴とする半導体パッケージ。2. A semiconductor package in which a large number of leads connected to pads of a substrate are arranged around a package body, and the package body has predetermined gaps with the substrate at four corners of the surface on the substrate side. A semiconductor package characterized in that projections facing each other are formed. 【請求項３】パッケージ本体の周囲に基板のパッドに接
続される多数本のリードを配設してなる半導体パッケー
ジであって、前記パッケージ本体の四隅に前記パッドに
接続される補強用リードを形成したことを特徴とする半
導体パッケージ。3. A semiconductor package in which a large number of leads connected to pads of a substrate are arranged around a package body, and reinforcing leads connected to the pads are formed at four corners of the package body. A semiconductor package characterized by the above. 【請求項４】前記補強用リードが接続される前記パッド
はグランド端子であることを特徴とする請求項３記載の
半導体パッケージ。4. The semiconductor package according to claim 3, wherein the pad to which the reinforcing lead is connected is a ground terminal.
JP19972893A 1993-08-11 1993-08-11 Semiconductor package Pending JPH0758247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19972893A JPH0758247A (en) 1993-08-11 1993-08-11 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19972893A JPH0758247A (en) 1993-08-11 1993-08-11 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH0758247A true JPH0758247A (en) 1995-03-03

Family

ID=16412633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19972893A Pending JPH0758247A (en) 1993-08-11 1993-08-11 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH0758247A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266650A (en) * 2007-07-20 2007-10-11 Texas Instr Japan Ltd Semiconductor device
US8139369B2 (en) 2008-04-14 2012-03-20 Lockheed Martin Corporation Printed wiring board solder pad arrangement
CN104347570A (en) * 2013-07-26 2015-02-11 飞思卡尔半导体公司 Leadless type semiconductor package and assembly method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266650A (en) * 2007-07-20 2007-10-11 Texas Instr Japan Ltd Semiconductor device
US8139369B2 (en) 2008-04-14 2012-03-20 Lockheed Martin Corporation Printed wiring board solder pad arrangement
CN104347570A (en) * 2013-07-26 2015-02-11 飞思卡尔半导体公司 Leadless type semiconductor package and assembly method thereof

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