JPH04253349A - Internal connection structure of semiconductor device - Google Patents
Internal connection structure of semiconductor deviceInfo
- Publication number
- JPH04253349A JPH04253349A JP3009414A JP941491A JPH04253349A JP H04253349 A JPH04253349 A JP H04253349A JP 3009414 A JP3009414 A JP 3009414A JP 941491 A JP941491 A JP 941491A JP H04253349 A JPH04253349 A JP H04253349A
- Authority
- JP
- Japan
- Prior art keywords
- upper electrode
- electrode
- semiconductor chip
- solder
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000005452 bending Methods 0.000 claims abstract description 3
- 230000000630 rising effect Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 21
- 238000005476 soldering Methods 0.000 abstract description 14
- 238000003754 machining Methods 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 238000007665 sagging Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、複数のダイオード,
サイリスタなどで構成された半導体モジュールを対象と
する半導体装置の内部接続構造に関する。[Industrial Application Field] The present invention is directed to a plurality of diodes,
The present invention relates to an internal connection structure of a semiconductor device, which is a semiconductor module composed of a thyristor or the like.
【0002】0002
【従来の技術】まず、頭記したダイオードモジュールを
例に、従来における半導体装置の構成を図3ないし図5
に示して説明する。図において、1は放熱ベース板、2
は絶縁基板、3は絶縁基板2の上に左右に並べて装着し
た半導体チップ(ダイオード)、4は半導体チップ3の
上に接合したコ字形の上部電極、5,6,7は接続端子
、8は外囲ケースである。なお、上部電極4,各接続端
子5,6,7は、銅板などを素材にプレス加工により所
定の形状に成形して作られたものである。また、前記の
接続端子5,6,7のうち、接続端子5は右側の半導体
チップ3のマウント用ベースを兼ね、接続端子6は上部
電極4を介して左側に並ぶ半導体チップ3に接続され、
接続端子7は左側の半導体チップ3のマウント用ベース
,および左右の半導体チップを直列接続する接続導体を
兼ねるようにして内部配線されており、かつ各接続端子
5,6,7は外囲ケース8を貫通して外部導出端子とな
る。なお、上記構成のダイオードモジュールの等価回路
を図4に示す。[Prior Art] First, the configuration of a conventional semiconductor device is shown in FIGS. 3 to 5, taking the above-mentioned diode module as an example.
This is shown and explained below. In the figure, 1 is a heat dissipation base plate, 2
3 is an insulating substrate, 3 is a semiconductor chip (diode) mounted side by side on the insulating substrate 2, 4 is a U-shaped upper electrode bonded on the semiconductor chip 3, 5, 6, 7 is a connection terminal, and 8 is a It is an outer case. Note that the upper electrode 4 and each of the connection terminals 5, 6, and 7 are made of a material such as a copper plate and formed into a predetermined shape by press working. Further, among the connection terminals 5, 6, and 7, the connection terminal 5 also serves as a mounting base for the semiconductor chip 3 on the right side, and the connection terminal 6 is connected to the semiconductor chips 3 arranged on the left side via the upper electrode 4,
The connection terminal 7 is internally wired so as to serve as a mounting base for the semiconductor chip 3 on the left side and a connection conductor for connecting the left and right semiconductor chips in series, and each connection terminal 5, 6, 7 is connected to the outer case 8. It passes through and becomes an external lead terminal. Incidentally, an equivalent circuit of the diode module having the above configuration is shown in FIG.
【0003】上記のダイオードモジュールは次のように
して組立られる。まず、半導体チップ3を個々に接続端
子5,および7の上に半田付けしてマウントし、さらに
半導体チップ3の上に上部電極4を半田付けして単体を
組み立てる。次に前記の各単体を放熱ベース1と接合し
た絶縁基板2上の所定位置に並べて接合するとともに、
左側の半導体チップ3をマウントした接続端子7の先端
を右側の半導体チップ3の上部電極4の上面に重ね合わ
せて両者間を半田付けを行い、さらに左側の半導体チッ
プ3の上部電極4の上面に接続端子6を半田付けする。
その後に外囲ケース8を被せ、さらにケースの内方に封
止樹脂(例えばシリコーンゲル)を充填してモジュール
組立品を完成する。The above diode module is assembled as follows. First, the semiconductor chip 3 is individually soldered and mounted on the connection terminals 5 and 7, and then the upper electrode 4 is soldered onto the semiconductor chip 3 to assemble a single unit. Next, each of the above-mentioned units is lined up and bonded at a predetermined position on the insulating substrate 2 bonded to the heat dissipation base 1, and
The tip of the connection terminal 7 on which the semiconductor chip 3 on the left is mounted is overlapped with the top surface of the upper electrode 4 of the semiconductor chip 3 on the right, and soldered between them, and then the top of the upper electrode 4 of the semiconductor chip 3 on the left is placed on the top surface of the upper electrode 4 of the semiconductor chip 3 on the left. Solder the connection terminal 6. Thereafter, an outer case 8 is placed on the module, and the inside of the case is filled with a sealing resin (for example, silicone gel) to complete the module assembly.
【0004】0004
【発明が解決しようとする課題】ところで、前記した半
導体装置の内部接続構造では、上部電極4と接続端子と
の間の半田付け、特に接続端子7との間の半田付け性に
問題点が残る。すなわち、先記したモジュールの組立方
法で上部電極4と接続端子7との間を半田付けする際に
良好な半田接合状態を確保するには、絶縁基板2の上に
並べて左右の半導体チップ3を取付けた組立状態で、接
続端子7の導体片と上部電極4の上面とが互いに密着す
るように重なり合っていることが必要である。しかして
、プレス加工などにより曲げ成形された上部電極,接続
端子などの部品は寸法,形状にバラツキがあり、また成
形後の部品取扱い時に変形の生じることがある。However, in the internal connection structure of the semiconductor device described above, there remains a problem in soldering between the upper electrode 4 and the connection terminal, especially in the solderability between the connection terminal 7. . That is, in order to ensure a good solder joint state when soldering between the upper electrode 4 and the connecting terminal 7 using the above-mentioned module assembly method, the left and right semiconductor chips 3 are placed side by side on the insulating substrate 2. It is necessary that the conductor piece of the connecting terminal 7 and the upper surface of the upper electrode 4 overlap each other so as to be in close contact with each other in the assembled state. However, parts such as upper electrodes and connection terminals that are bent and formed by press working etc. have variations in size and shape, and deformation may occur when the parts are handled after being formed.
【0005】したがって、図6で示すように接続端子7
と上部電極4との間での半田付けに際し、上部電極4の
高さ寸法hにバラツキ,変形(コ字形上部電極4の上辺
4aと下辺4bのいずれかが傾いている)があると、上
部電極4の上面と接続端子7の面との間で平行度が得ら
れず、両者間の半田付け面に隙間が生じるようになる。
このために、半田付けした状態では半田層9が図示のよ
うな形態となって半田付け不良となり、熱的,機械的な
ストレスが加わると半田接合部が剥離するなどして製品
の信頼性が大幅に低下する。また、半田付け面の隙間を
埋めるように半田量を増量すると、隙間があるために半
田が半導体チップ3の上に垂れ落ちてチップ特性の不良
を引き起こすおそれがある。Therefore, as shown in FIG.
When soldering between the upper electrode 4 and the upper electrode 4, if there is variation or deformation in the height dimension h of the upper electrode 4 (either the upper side 4a or the lower side 4b of the U-shaped upper electrode 4 is inclined), the upper Parallelism cannot be obtained between the upper surface of the electrode 4 and the surface of the connection terminal 7, and a gap is created between the two on the soldering surface. For this reason, in the soldered state, the solder layer 9 takes the form shown in the figure, resulting in poor soldering, and when thermal or mechanical stress is applied, the solder joints peel off, reducing the reliability of the product. significantly reduced. Furthermore, if the amount of solder is increased to fill the gap on the soldering surface, there is a risk that the solder will drip onto the semiconductor chip 3 due to the gap, causing defective chip characteristics.
【0006】本発明は上記の点にかんがみなされたもの
であり、上部電極と接続端子との間を半田付けする際に
、各部品の寸法,形状にバラツキ,変形があっても、こ
れらの寸法誤差,変形を補償して良好な半田付け状態が
確保できるようにした半導体装置の内部接続構造を提供
することを目的とする。The present invention has been made in consideration of the above points, and even if there are variations or deformations in the dimensions and shapes of each component when soldering between the upper electrode and the connection terminal, these dimensions can be fixed. It is an object of the present invention to provide an internal connection structure for a semiconductor device that can compensate for errors and deformation and ensure a good soldering condition.
【0007】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明は、先記したダイオードモジュールなどを対
象に、半導体チップの上部電極に対してその上面側に接
続端子が嵌まり込む溝部を形成し、この溝部に接続端子
を入り込ませて半田付けを行うものとする。[Means for Solving the Problems] In order to solve the above problems, the present invention targets the above-mentioned diode module, etc., and provides a groove portion into which a connecting terminal fits into the upper surface side of the upper electrode of the semiconductor chip. A connection terminal is inserted into this groove and soldered.
【0008】また、上記の構成における溝部は、上部電
極の上面と上面の左右両側縁から上方に起立した側壁部
との間に形成されたものであり、かつ該側壁部は折り曲
げ加工によって成形することができる。Furthermore, the groove in the above structure is formed between the upper surface of the upper electrode and the side wall portions rising upward from the left and right edges of the upper surface, and the side wall portions are formed by bending. be able to.
【0009】[0009]
【作用】上記の構成により、上部電極の上に接続端子を
重ねて両者間を半田付けする際に、各部品に多少の寸法
バラツキ,変形があっても、接続端子は溝部内に入り込
んで上部電極と対面しているので、半田量が十分であれ
ば溝内に保持された半田で両者の間が正常に半田接合さ
れる。しかも前記溝部は溶融半田のはみ出し,垂れ流れ
を阻止するように働くので、半田量を多少増量しても余
分な半田が半導体チップの上に垂れ落ちるおそれはない
。[Function] With the above configuration, when stacking the connecting terminal on top of the upper electrode and soldering between them, even if there is some dimensional variation or deformation of each part, the connecting terminal will fit into the groove and Since it faces the electrode, if the amount of solder is sufficient, the solder held in the groove will normally solder connect the two. Moreover, since the groove functions to prevent the molten solder from spilling out or dripping, even if the amount of solder is increased somewhat, there is no risk of excess solder dripping onto the semiconductor chip.
【0010】0010
【実施例】図1,図2は図3に示したダイオードモジュ
ールを実施対象とする本発明の実施例を示すものであり
、図3,図4に対応する同一部材には同じ符号が付して
ある。すなわち、半導体チップ3の上に取付けたコ字形
の上部電極4には、その上辺4aの左右側縁から上方に
向けて直角に立ち上がる側壁部4c,4dが曲げ加工さ
れ、この左右側壁部4c,4dと電極4の上面との間に
U字状の溝部4eが形成されている。また、この溝部4
eの溝幅は上部電極4と半田接合し合う相手側の接続電
極7の寸法(電極導体片の幅)に合わせて選定されてい
る。そして、上部電極4に接続電極6,7を半田付けす
る際には、接続電極を前記した左右の側壁部4cと4d
の間に入り込ませて溝部4e内に嵌合し、この状態で上
部電極4と接続電極7との間を半田付けを施す。[Embodiment] FIGS. 1 and 2 show an embodiment of the present invention which is applied to the diode module shown in FIG. 3, and the same members corresponding to FIGS. There is. That is, the U-shaped upper electrode 4 mounted on the semiconductor chip 3 has side wall portions 4c and 4d that rise upward at right angles from the left and right edges of the upper side 4a, and are bent. A U-shaped groove 4e is formed between the electrode 4d and the upper surface of the electrode 4. Moreover, this groove portion 4
The groove width e is selected in accordance with the dimensions (width of the electrode conductor piece) of the mating connection electrode 7 that is soldered to the upper electrode 4. When soldering the connection electrodes 6 and 7 to the upper electrode 4, the connection electrodes are attached to the left and right side walls 4c and 4d.
In this state, the upper electrode 4 and the connecting electrode 7 are soldered together.
【0011】[0011]
【発明の効果】以上述べたように、本発明の内部接続構
造によれば、上部電極の上に接続端子を重ねて両者間を
半田付けする際に、各部品に多少の寸法バラツキ,変形
があっても、半田量が十分であれば溝内に保持された半
田で両者の間を正常に半田接合することができる。しか
も前記溝部により溶融半田のはみ出し,垂れ流れが阻止
されるので、半田量を増量しても余分な半田が半導体チ
ップの上に垂れ落ちるおそれはなく、これにより半田付
けの作業性の改善が図れる。[Effects of the Invention] As described above, according to the internal connection structure of the present invention, when the connection terminal is stacked on the upper electrode and the two are soldered, there is no possibility of slight dimensional variation or deformation of each component. Even if there is, if the amount of solder is sufficient, the solder held in the groove can successfully solder connect the two. Furthermore, the groove prevents the molten solder from protruding or dripping, so even if the amount of solder is increased, there is no risk of excess solder dripping onto the semiconductor chip, thereby improving soldering workability. .
【図1】本発明実施例の内部接続構造を示す要部構造の
分解斜視図[Fig. 1] An exploded perspective view of the main structure showing the internal connection structure of the embodiment of the present invention.
【図2】図1の内部接続構造を採用した半導体装置の組
立図[Figure 2] Assembly diagram of a semiconductor device adopting the internal connection structure shown in Figure 1
【図3】従来における半導体装置の組立構成図[Figure 3] Assembly configuration diagram of a conventional semiconductor device
【図4】
図3の等価回路図[Figure 4]
Equivalent circuit diagram of Figure 3
【図5】図3における要部構造の分解斜視図[Figure 5] Exploded perspective view of the main structure in Figure 3
【図6】図
5で半田付けを施した状態を表す図[Figure 6] Diagram showing the soldered state in Figure 5
3 半導体チップ 4 上部電極 4a 上辺 4c 側壁部 4d 側壁部 4e 溝部 6 接続端子 7 接続端子 3 Semiconductor chip 4 Upper electrode 4a Top side 4c Side wall part 4d Side wall part 4e Groove 6 Connection terminal 7 Connection terminal
Claims (3)
載, 接合し、該上部電極の上面に接続端子を重ね合わ
せて半田付けした半導体装置において、上部電極の上面
側に接続端子が嵌まり込む溝部を形成したことを特徴と
する半導体装置の内部接続構造。Claim 1: A semiconductor device in which a U-shaped upper electrode is mounted and bonded on a semiconductor chip, and a connecting terminal is overlaid and soldered on the upper surface of the upper electrode, wherein the connecting terminal is fitted onto the upper surface of the upper electrode. An internal connection structure for a semiconductor device, characterized by forming a groove into which the semiconductor device fits.
溝部が、上部電極の上面と上面の左右両側縁から上方に
起立した側壁部の間に形成されていることを特徴とする
半導体装置の内部接続構造。2. The internal connection structure according to claim 1,
1. An internal connection structure for a semiconductor device, wherein a groove portion is formed between an upper surface of an upper electrode and side wall portions rising upward from both left and right edges of the upper surface.
側壁部を折り曲げ加工により成形したことを特徴とする
半導体装置の内部接続構造。3. The internal connection structure according to claim 2,
An internal connection structure for a semiconductor device, characterized in that a side wall portion is formed by bending.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3009414A JP2782640B2 (en) | 1991-01-30 | 1991-01-30 | Internal connection structure of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3009414A JP2782640B2 (en) | 1991-01-30 | 1991-01-30 | Internal connection structure of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04253349A true JPH04253349A (en) | 1992-09-09 |
JP2782640B2 JP2782640B2 (en) | 1998-08-06 |
Family
ID=11719732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3009414A Expired - Lifetime JP2782640B2 (en) | 1991-01-30 | 1991-01-30 | Internal connection structure of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2782640B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004506326A (en) * | 2000-08-04 | 2004-02-26 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for electrically connecting a semiconductor component to an electrical component group |
WO2019176199A1 (en) * | 2018-03-14 | 2019-09-19 | 三菱電機株式会社 | Semiconductor power module and power conversion device |
-
1991
- 1991-01-30 JP JP3009414A patent/JP2782640B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004506326A (en) * | 2000-08-04 | 2004-02-26 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for electrically connecting a semiconductor component to an electrical component group |
JP4800556B2 (en) * | 2000-08-04 | 2011-10-26 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for electrically connecting a semiconductor component with an electrical component group |
WO2019176199A1 (en) * | 2018-03-14 | 2019-09-19 | 三菱電機株式会社 | Semiconductor power module and power conversion device |
JPWO2019176199A1 (en) * | 2018-03-14 | 2021-01-07 | 三菱電機株式会社 | Semiconductor power modules and power converters |
Also Published As
Publication number | Publication date |
---|---|
JP2782640B2 (en) | 1998-08-06 |
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