JPH0247109B2 - JUSHIFUSHIGATAMOJUURU - Google Patents

JUSHIFUSHIGATAMOJUURU

Info

Publication number
JPH0247109B2
JPH0247109B2 JP59205022A JP20502284A JPH0247109B2 JP H0247109 B2 JPH0247109 B2 JP H0247109B2 JP 59205022 A JP59205022 A JP 59205022A JP 20502284 A JP20502284 A JP 20502284A JP H0247109 B2 JPH0247109 B2 JP H0247109B2
Authority
JP
Japan
Prior art keywords
signal terminal
cathode
resin
plate
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59205022A
Other languages
Japanese (ja)
Other versions
JPS6184047A (en
Inventor
Masanori Nakatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59205022A priority Critical patent/JPH0247109B2/en
Publication of JPS6184047A publication Critical patent/JPS6184047A/en
Publication of JPH0247109B2 publication Critical patent/JPH0247109B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は複数個の半導体チツプを樹脂封止し
た樹脂封止形モジユールに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed module in which a plurality of semiconductor chips are sealed with resin.

〔従来の技術〕[Conventional technology]

以下、2個のサイリスタチツプを樹脂封止した
樹脂封止形の電力用サイリスタモジユールを例に
とり説明する。
Hereinafter, a resin-sealed power thyristor module in which two thyristor chips are sealed with resin will be described as an example.

第2図Aは従来の電力用サイリスタモジユール
の樹脂封止前の状態を示す平面図、第2図Bは第
2図AのB−B線での断面図である。
FIG. 2A is a plan view showing a conventional power thyristor module before being sealed with resin, and FIG. 2B is a sectional view taken along the line BB in FIG. 2A.

図において、1は金属板からなる放熱板、2は
セラミツクス板からなり放熱板1の上面の一部分
上に固着された絶縁基板、3aおよび3bはそれ
ぞれ金属板からなり一方の端部側が絶縁基板2の
上面の右端側の部分上および左端側の部分上に互
いの間に間隔をおいて固着され他方の端部側が絶
縁基板2の上面の右端縁および左端縁から上方に
伸びるようにL字形状に折り曲げられ絶縁基板2
の上面に固着された部分上に後述のサイリスタチ
ツプの陽極板がろう付けされる陽極引き出し板、
4aおよび4bは一方の主面の中心部に形成され
たゲート電極とゲート電極形成部分以外の部分に
ゲート電極を取り囲んで形成された陰極と他方の
主面部に形成された陽極とを有するサイリスタチ
ツプ、5aおよび5bはそれぞれモリブデン板か
らなりサイリスタチツプ4a,4bの陽極に上面
がろう付けされ下面が陽極引き出し板3a,3b
の絶縁基板2に固着された部分上にろう付けされ
た陽極板、6aおよび6bはそれぞれ金属棒から
なりサイリスタチツプ4a,4bのゲート電極に
一方の端部がろう付けされたゲートリード、7a
および7bはそれぞれ金属板からなり中央部がサ
イリスタチツプ4a,4bの陰極にろう付けされ
両端部が上方に折り曲げられたU字形状の陰極
板、8aおよび8bはそれぞれ金属板からなり陰
極板7aの左側の端部および陰極板7bの右側の
端部に一方の端部が溶接された陰極引き出し板、
9aおよび9bはそれぞれ絶縁材料からなり放熱
板1の上面の絶縁基板2の左外側の部分上にサイ
リスタチツプ4a,4bの配列方向と直角方向に
互いの間に間隔をおいて対向するように固着され
サイリスタチツプ4aのゲート・陰極間およびサ
イリスタチツプ4bのゲート・陰極間への作動信
号印加用の信号端子板を保持する信号端子板保持
台、10aおよび11aはそれぞれ金属板からな
り互いの間に間隔をおいて下端部側が信号端子板
保持台9aの信号端子板保持台9b側とは反対側
の側面から外部へ突出し上端部側が信号端子板保
持台9aの上面から上方に伸びるように信号端子
板保持台9aに保持されゲートリード6aに接続
されるゲート信号端子板および陰極板7aに接続
される陰極信号端子板、10bおよび11bはそ
れぞれゲート信号端子板10aおよび陰極信号端
子板11aと同様に信号端子板保持台9bに保持
されゲートリード6bに接続されるゲート信号端
子板および陰極板7bに接続される陰極信号端子
板、12aおよび12bはそれぞれ金属細線から
なり一方の端部がゲートリード6aおよびゲート
リード6bに半田付けされ他方の端部がゲート信
号端子板10aの下端部およびゲート信号端子板
10bの下端部に半田付けされた第1および第2
のゲート配線、13aおよび13bはそれぞれゲ
ート配線12a,12bと同様に一方の端部が陰
極板7aの右側の端部および陰極板7bの左側の
端部に半田付けされ他方の端部が陰極信号端子板
11aの下端部および陰極信号端子板11bの下
端部に半田付けされた第1および第2の陰極配
線、14は絶縁基板2、陽極引き出し板3a,3
bの所要部分、サイリスタチツプ4a,4b、陽
極板5a,5b、ゲートリード6a,6b、陰極
板7a,7b、陰極引き出し板8a,8bの所要
部分、信号端子板保持台9a,9b、ゲート信号
端子板10a,10bの所要部分、陰極信号端子
板11a,11bの所要部分、ゲート配線12
a,12bおよび陰極配線13a,13bを取り
囲んで下端面が放熱板1の上面に固着された樹脂
容器である。
In the figure, 1 is a heat dissipation plate made of a metal plate, 2 is an insulating substrate made of a ceramic plate and fixed on a part of the upper surface of the heat dissipation plate 1, and 3a and 3b are each made of a metal plate, and one end side is an insulating substrate 2. L-shaped parts are fixed on the right and left parts of the upper surface with a space between them, and the other end extends upward from the right and left edges of the upper surface of the insulating substrate 2. Insulated board 2
an anode pull-out plate on which the anode plate of the thyristor chip, which will be described later, is brazed onto the part fixed to the top surface;
4a and 4b are thyristor chips having a gate electrode formed at the center of one main surface, a cathode formed surrounding the gate electrode in a part other than the gate electrode forming part, and an anode formed at the other main surface. , 5a and 5b are respectively made of molybdenum plates, and the upper surfaces are brazed to the anodes of the thyristor chips 4a and 4b, and the lower surfaces are the anode drawer plates 3a and 3b.
An anode plate 6a and 6b are each made of a metal rod, and a gate lead 7a has one end brazed to the gate electrode of the thyristor chips 4a and 4b.
and 7b are metal plates each having a U-shaped cathode plate whose central part is brazed to the cathodes of thyristor chips 4a and 4b and whose both ends are bent upwards; 8a and 8b are metal plates each and which is a U-shaped cathode plate whose central part is brazed to the cathodes of thyristor chips 4a and 4b; a cathode drawer plate, one end of which is welded to the left end and the right end of the cathode plate 7b;
9a and 9b are each made of an insulating material and are fixed on the left outer part of the insulating substrate 2 on the upper surface of the heat sink 1 so as to face each other with a gap in the direction perpendicular to the arrangement direction of the thyristor chips 4a and 4b. The signal terminal plate holders 10a and 11a, each of which holds a signal terminal plate for applying an operating signal between the gate and the cathode of the thyristor chip 4a and between the gate and the cathode of the thyristor chip 4b, are each made of a metal plate and have a metal plate between them. The signal terminals are arranged at intervals such that the lower end side protrudes outward from the side of the signal terminal board holder 9a opposite to the signal terminal board holder 9b side, and the upper end side extends upward from the upper surface of the signal terminal board holder 9a. The gate signal terminal plate held by the plate holder 9a and connected to the gate lead 6a and the cathode signal terminal plate 10b and 11b connected to the cathode plate 7a are the same as the gate signal terminal plate 10a and the cathode signal terminal plate 11a, respectively. The gate signal terminal plate held by the signal terminal plate holder 9b and connected to the gate lead 6b and the cathode signal terminal plate 12a and 12b connected to the cathode plate 7b are each made of thin metal wire, and one end thereof is connected to the gate lead 6a. and first and second leads soldered to the gate lead 6b, the other end of which is soldered to the lower end of the gate signal terminal board 10a and the lower end of the gate signal terminal board 10b.
The gate wirings 13a and 13b have one end soldered to the right end of the cathode plate 7a and the left end of the cathode plate 7b, respectively, like the gate wirings 12a and 12b, and the other end soldered to the cathode signal. First and second cathode wirings are soldered to the lower end of the terminal board 11a and the lower end of the cathode signal terminal board 11b; reference numeral 14 denotes an insulating substrate 2; anode lead-out plates 3a and 3;
Required parts of b, thyristor chips 4a, 4b, anode plates 5a, 5b, gate leads 6a, 6b, cathode plates 7a, 7b, required parts of cathode pull-out plates 8a, 8b, signal terminal board holder 9a, 9b, gate signal Required parts of terminal boards 10a and 10b, required parts of cathode signal terminal boards 11a and 11b, gate wiring 12
It is a resin container whose lower end surface is fixed to the upper surface of the heat sink 1, surrounding the cathode wires 13a, 12b and the cathode wires 13a, 13b.

この従来の電力用サイリスタモジユールは、図
示の状態に組立てた後に、樹脂容器14内に封止
用樹脂を注入すると、完成される。
This conventional power thyristor module is completed by injecting a sealing resin into the resin container 14 after assembling it in the state shown.

従来の電力用サイリスタモジユールは上記のよ
うに構成されているので、ゲート信号端子板10
aと陰極信号端子板11aとの間にゲート信号を
印加することによつてサイリスタチツプ4aが作
動し、ゲート信号端子板10bと陰極信号端子板
11bとの間にゲート信号を印加することによつ
てサイリスタチツプ4bが作動する。
Since the conventional power thyristor module is configured as described above, the gate signal terminal board 10
The thyristor chip 4a is activated by applying a gate signal between the gate signal terminal plate 10b and the cathode signal terminal plate 11a, and the thyristor chip 4a is activated by applying a gate signal between the gate signal terminal plate 10b and the cathode signal terminal plate 11b. The thyristor chip 4b then operates.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の電力用サイリスタモジユー
ルでは、ゲート配線12aおよび陰極配線13a
の長さが長く(例えば10cm程度)なるので、これ
らの配線12a,13aがサイリスタチツプ4b
に近接すると、サイリスタチツプ4bの陽極・陰
極間を流れる主電流による配線12a,13aへ
の電磁誘導によつてサイリスタチツプ4aが誤動
作するおそれがある。また、配線12a,12
b,13a,13bの配線後の工程において、こ
れらの配線12a,12b,13a,13bに傷
ができると、これらの配線12a,12b,13
a,13bに断線が生ずるおそれがあり、信頼性
が悪いという問題点があつた。また、信号端子板
保持台9a,9bを絶縁基板2の上面上に位置決
めして固着する必要がある。さらに、ゲート配線
12a,12bの両端部をそれぞれゲートリード
6a,6bおよびゲート信号端子板10a,10
bに位置決めして半田付けし、陰極配線13a,
13bの両端部をそれぞれ陰極板7a,7bおよ
び陰極信号端子板11a,11bに位置決めして
半田付けしなければならず、組立て作業性が極め
て悪いとという問題点があつた。
In the conventional power thyristor module as described above, the gate wiring 12a and the cathode wiring 13a
Since the length of the thyristor chip 4b is long (for example, about 10 cm), these wirings 12a and 13a are connected to the thyristor chip 4b.
If the thyristor chip 4b is brought close to the thyristor chip 4b, there is a risk that the thyristor chip 4a may malfunction due to electromagnetic induction to the wirings 12a and 13a due to the main current flowing between the anode and cathode of the thyristor chip 4b. In addition, the wiring 12a, 12
If these wirings 12a, 12b, 13a, 13b are damaged in the process after wiring wiring 12a, 13a, 13b, these wirings 12a, 12b, 13
There was a problem that there was a risk of wire breakage occurring in a and 13b, resulting in poor reliability. Further, it is necessary to position and fix the signal terminal plate holding stands 9a and 9b on the upper surface of the insulating substrate 2. Further, both ends of the gate wirings 12a, 12b are connected to gate leads 6a, 6b and gate signal terminal boards 10a, 10, respectively.
Position and solder the cathode wiring 13a,
Both ends of 13b had to be positioned and soldered to cathode plates 7a, 7b and cathode signal terminal plates 11a, 11b, respectively, resulting in a problem that assembly workability was extremely poor.

この発明は、かかる問題点を解決するためにな
されたもので、信頼性がよく、しかも組立て作業
性の極めてよい樹脂封止形モジユールを得ること
を目的とする。
The present invention has been made to solve these problems, and an object of the present invention is to provide a resin-sealed module that is highly reliable and extremely easy to assemble.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る樹脂封止形モジユールは、制御
電極と第1および第2の主電極とを有する複数個
の半導体チツプを収容する樹脂容器の容器壁内に
中央部が埋設され一方の端部が半導体チツプの制
御電極の上にこれと係合し半田付けが可能なよう
に伸び他方の端部が容器壁から樹脂容器内に出て
樹脂容器の上方に伸びるように形成され半導体チ
ツプの制御電極への作動信号が印加される制御電
極信号端子板を複数個の半導体チツプのそれぞれ
に設けたものである。
The resin-sealed module according to the present invention has a central portion embedded in a container wall of a resin container housing a plurality of semiconductor chips having a control electrode and first and second main electrodes, and one end portion of the resin-sealed module. The control electrode of the semiconductor chip is formed such that it extends over the control electrode of the semiconductor chip so that it can be engaged with and soldered to, and the other end extends from the container wall into the resin container and extends above the resin container. Each of the plurality of semiconductor chips is provided with a control electrode signal terminal plate to which an activation signal is applied.

〔作用〕[Effect]

この発明においては、制御電極信号端子板の長
さが長い場合であつても、この制御電極信号端子
板の中央部が樹脂容器の容器壁内に埋設されてい
るので、この制御電極信号端子板がこれが接続さ
れた半導体チツプ以外の半導体チツプに近接する
おそれがないから、この制御電極信号端子板が接
続された半導体チツプがこの半導体チツプ以外の
半導体チツプの第1および第2の主電極間を流れ
る主電流による電磁誘導によつて誤動作すること
がなく、またこの制御電極信号端子板に傷ができ
て断線が生ずるおそれもなく、信頼性が上記従来
装置の場合よりよくなる。さらに、上記従来装置
における信号端子板保持台および金属細線からな
る配線が不要となるから、組立て作業性が上記従
来装置の場合より極めて良くなる。
In this invention, even if the length of the control electrode signal terminal plate is long, the central part of the control electrode signal terminal plate is embedded in the container wall of the resin container. Since there is no risk that this control electrode signal terminal board will come close to a semiconductor chip other than the one to which it is connected, the semiconductor chip to which this control electrode signal terminal board is connected will not be able to connect between the first and second main electrodes of semiconductor chips other than this semiconductor chip. There is no malfunction due to electromagnetic induction caused by the flowing main current, and there is no risk of damage to the control electrode signal terminal plate and disconnection, resulting in better reliability than in the conventional device. Furthermore, since the signal terminal plate holder and the wiring made of thin metal wires in the conventional device are not required, the assembly workability is much better than in the conventional device.

〔実施例〕〔Example〕

第1図Aはこの発明の一実施例の樹脂封止前の
状態を示す平面図、第1図Bは第1図AのB−
B線での断面図である。
FIG. 1A is a plan view showing a state before resin sealing of an embodiment of the present invention, and FIG. 1B is a B--FIG.
It is a sectional view taken along the B line.

図において、上記従来装置の符号と同一符号は
同等部分を示す。4aおよび4bはこの実施例で
の半導体チツプであるサイリスタチツプ、6aお
よび6bはこの実施例での制御電極であるゲート
リード、20aおよび20bはそれぞれ金属板か
らなり中央部が樹脂容器14のサイリスタチツプ
4a,4bの配列方向と直角方向の両容器壁内に
埋設され右側の端部がゲートリード6aおよびゲ
ートリード6bと係合し半田付けが可能なように
伸び左側の端部が樹脂容器14の絶縁基板2の左
外側の容器壁の部分から樹脂容器14内に出て樹
脂容器14の上方に伸びるように形成されゲート
リード6aおよびゲートリード6bへの作動信号
が印加されるこの実施例での制御電極信号端子板
である第1および第2のゲート信号端子板、21
aおよび21bはそれぞれゲート信号端子板20
a,20bと同様に樹脂容器14の容器壁内のゲ
ート信号端子板20aおよびゲート信号端子板2
0bとの間に間隔をおいたそれぞれの下の部分に
中央部が埋設され右側の端部が陰極板7aの右側
の端部および陰極板7bの左側の端部と係合し半
田付けが可能なように伸び左側の端部が樹脂容器
14の容器壁のゲート信号端子板20aおよびゲ
ート信号端子板20bとの間に間隔をおいたそれ
ぞれの左側の部分から樹脂容器14内に出て樹脂
容器14の上方に伸びるように形成され陰極板7
aおよび陰極板7bへの作動信号が印加される第
1および第2の陰極信号端子板である。
In the figure, the same reference numerals as those of the above-mentioned conventional device indicate equivalent parts. 4a and 4b are thyristor chips which are semiconductor chips in this embodiment, 6a and 6b are gate leads which are control electrodes in this embodiment, and 20a and 20b are thyristor chips each made of a metal plate and whose center part is a resin container 14. 4a and 4b are embedded in the walls of the container in the direction perpendicular to the arrangement direction of the resin container 14, and the right end engages with the gate leads 6a and 6b to enable soldering, and the left end extends into the resin container 14. In this embodiment, the insulating substrate 2 is formed to extend into the resin container 14 from the left outer container wall portion and extend above the resin container 14, and an actuation signal is applied to the gate lead 6a and the gate lead 6b. first and second gate signal terminal plates, 21, which are control electrode signal terminal plates;
a and 21b are gate signal terminal boards 20, respectively.
Gate signal terminal plate 20a and gate signal terminal plate 2 in the container wall of resin container 14 in the same manner as a and 20b.
The center part is buried in the lower part of each of the cathode plates 7a and 0b, and the right end part engages with the right end part of the cathode plate 7a and the left end part of the cathode plate 7b, and can be soldered. The left end extends into the resin container 14 from the respective left portions of the container wall of the resin container 14 with a gap between the gate signal terminal plate 20a and the gate signal terminal plate 20b. The cathode plate 7 is formed to extend upward from the cathode plate 14.
a and cathode plate 7b are first and second cathode signal terminal plates to which actuation signals are applied.

上記のように構成された電力用サイリスタモジ
ユールにおいては、ゲート信号端子板20aおよ
び陰極信号端子板21aの長さが長い場合であつ
ても、これらの信号端子板20a,21aの中央
部が樹脂容器14の容器壁内に埋設されているの
で、これらの信号端子板20a,21aがサイリ
スタチツプ4bに近接するおそれがないから、サ
イリスタチツプ4bの陽極・陰極間を流れる主電
流による電磁誘導によつてサイリスタチツプ4a
が誤動するおそれがなく、また信号端子板20
a,21a,20b,21bに傷ができて断線が
生ずるおそれもなく、信頼性が上記従来装置の場
合よりよくなる。さらに、上記従来装置における
信号端子板保持台9a,9bおよび金属細線から
配線12a,12b,13a,13bが不要とな
るから、組立て作業性が上記従来装置の場合によ
り極めてよくなる。
In the power thyristor module configured as described above, even if the gate signal terminal plate 20a and the cathode signal terminal plate 21a are long, the center portions of these signal terminal plates 20a and 21a are made of resin. Since these signal terminal boards 20a and 21a are buried in the wall of the container 14, there is no risk of them coming close to the thyristor chip 4b, so that they are not affected by electromagnetic induction caused by the main current flowing between the anode and cathode of the thyristor chip 4b. Thyristor chip 4a
There is no risk of malfunction, and the signal terminal board 20
There is no fear of damage to a, 21a, 20b, and 21b resulting in disconnection, and reliability is improved compared to the conventional device. Furthermore, since the signal terminal plate holding stands 9a, 9b and the wires 12a, 12b, 13a, 13b from the thin metal wires in the conventional device are no longer required, the assembly workability is much better than in the conventional device.

なお、この実施例では、陰極信号端子板21
a,21bを設けたが、必ずしもこれらは必要で
はなく、これらの陰極信号端子板21a,21b
を省略してもよい。この場合には、陰極信号端子
板21a,21bの替りに、陰極引き出し板8
a,8bを使用すればよい。
Note that in this embodiment, the cathode signal terminal plate 21
a, 21b are provided, but these are not necessarily necessary, and these cathode signal terminal plates 21a, 21b are provided.
may be omitted. In this case, instead of the cathode signal terminal plates 21a and 21b, the cathode drawer plate 8
a, 8b may be used.

また、この実施例では、樹脂封止形電力用サイ
リスタモジユールを例にとり述べたが、この発明
はこれに限らず、制御電極と第1および第2の主
電極とを有するトランジスタチツプなどのその他
の半導体チツプを用いる樹脂封止形モジユールに
も適用することができる。
Further, in this embodiment, a resin-sealed power thyristor module has been described as an example, but the present invention is not limited to this, and can be applied to other devices such as a transistor chip having a control electrode and first and second main electrodes. It can also be applied to a resin-sealed module using a semiconductor chip.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、制御電極と第
1および第2の主電極とを有する複数個の半導体
チツプを収容する樹脂容器の容器壁内に中央部が
埋設され一方の端部が半導体チツプの制御電極の
上にこれと係合し半田付けが可能なように伸び他
方の端部が容器壁から樹脂容器内に出て樹脂容器
の上方に伸びるように形成され半導体チツプの制
御電極への作動信号が印加される制御電極信号端
子板を複数個の半導体チツプのそれぞれに設けた
ので、制御電極信号端子板の長さが長い場合であ
つても、この制御電極信号端子板の中央部が樹脂
容器の容器壁内に埋設されていることにより、こ
の制御電極信号端子板がこれが接続された半導体
チツプ以外の半導体チツプに近接するおそれがな
いから、この制御電極信号端子板が接続された半
導体チツプがこの半導体チツプ以外の半導体チツ
プの第1および第2の主電極間を流れる主電流に
よる電磁誘導によつて誤動作することがなく、ま
たこの制御電極信号端子板に傷ができて断線が生
ずるおそれもなく、信頼性が上記従来装置の場合
よりよくなる。さらに、上記従来装置における信
号端子保持台および金属細線からなる配線が不要
となるから、組立て作業性が上記従来装置の場合
より極めてよくなる。
As explained above, the present invention has a central portion embedded in the container wall of a resin container that accommodates a plurality of semiconductor chips having a control electrode and first and second main electrodes, and one end portion of which contains a plurality of semiconductor chips. It extends over the control electrode so that it can be engaged with and soldered to, and the other end extends from the container wall into the resin container and extends above the resin container, and is actuated to the control electrode of the semiconductor chip. Since a control electrode signal terminal plate to which a signal is applied is provided on each of the plurality of semiconductor chips, even if the control electrode signal terminal plate is long, the center part of the control electrode signal terminal plate is made of resin. Since this control electrode signal terminal plate is embedded in the container wall of the container, there is no risk that the control electrode signal terminal plate will come close to a semiconductor chip other than the semiconductor chip to which this control electrode signal terminal plate is connected. There is no risk of malfunction due to electromagnetic induction due to the main current flowing between the first and second main electrodes of semiconductor chips other than this semiconductor chip, and there is no risk of damage to the control electrode signal terminal plate and disconnection. Therefore, the reliability is better than that of the conventional device. Furthermore, since the signal terminal holder and the wiring made of thin metal wires in the conventional device are not required, the assembly workability is much better than in the conventional device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図Aはこの発明の一実施例の樹脂封止前の
状態を示す平面図、第1図Bは第1図AのB−
B線での断面図、第2図Aは従来の電力用サイ
リスタモジユールの樹脂封止前の状態を示す平面
図、第2図Bは第2図AのB−B線での断面
図である。 図において、1は放熱板、2は絶縁基板、4a
および4bは半導体チツプ(サイリスタチツプ)、
6aおよび6bは制御電極(ゲートリード)、2
0aおよび20bは制御電極信号端子板(ゲート
信号端子板)である。なお、各図中同一符号は同
一または相当部分を示す。
FIG. 1A is a plan view showing a state before resin sealing of an embodiment of the present invention, and FIG. 1B is a B--FIG.
Figure 2A is a plan view of a conventional power thyristor module before being sealed with resin, and Figure 2B is a cross-sectional view taken along line B-B of Figure 2A. be. In the figure, 1 is a heat sink, 2 is an insulating substrate, and 4a
and 4b is a semiconductor chip (thyristor chip),
6a and 6b are control electrodes (gate leads), 2
0a and 20b are control electrode signal terminal plates (gate signal terminal plates). Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 放熱板の上面の一部分上に固着された絶縁基
板の上面に互いの間に間隔をおいて固着され制御
電極と第1および第2の主電極とを有する複数個
の半導体チツプ、上記絶縁基板および上記複数個
の半導体チツプを取り囲んで下端面が上記放熱板
の上面に固着された樹脂容器、並びに上記複数個
の半導体チツプのそれぞれに対応して設けられ中
央部が上記樹脂容器の容器壁内に埋設され一方の
端部が当該半導体チツプの制御電極の上にこれと
係合し半田付けが可能なように伸び他方の端部が
上記容器壁から上記樹脂容器内に出て上記樹脂容
器の上方に伸びるように形成された上記当該半導
体チツプへの作動信号印加用の制御電極信号端子
板を備えた樹脂封止形モジユール。
1 a plurality of semiconductor chips having a control electrode and first and second main electrodes fixed to the upper surface of an insulating substrate fixed to a portion of the upper surface of the heat sink with a space therebetween; the above-mentioned insulating substrate; and a resin container surrounding the plurality of semiconductor chips and having a lower end surface fixed to the upper surface of the heat sink, and a resin container provided corresponding to each of the plurality of semiconductor chips and having a central portion within the container wall of the resin container. The chip is embedded in the resin container with one end extending over the control electrode of the semiconductor chip to enable soldering, and the other end extending from the container wall into the resin container. A resin-sealed module comprising a control electrode signal terminal plate extending upward for applying an actuation signal to the semiconductor chip.
JP59205022A 1984-09-29 1984-09-29 JUSHIFUSHIGATAMOJUURU Expired - Lifetime JPH0247109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59205022A JPH0247109B2 (en) 1984-09-29 1984-09-29 JUSHIFUSHIGATAMOJUURU

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59205022A JPH0247109B2 (en) 1984-09-29 1984-09-29 JUSHIFUSHIGATAMOJUURU

Publications (2)

Publication Number Publication Date
JPS6184047A JPS6184047A (en) 1986-04-28
JPH0247109B2 true JPH0247109B2 (en) 1990-10-18

Family

ID=16500144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59205022A Expired - Lifetime JPH0247109B2 (en) 1984-09-29 1984-09-29 JUSHIFUSHIGATAMOJUURU

Country Status (1)

Country Link
JP (1) JPH0247109B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235658A (en) * 1985-08-09 1987-02-16 Fuji Electric Co Ltd Semiconductor device
EP0609528A1 (en) * 1993-02-01 1994-08-10 Motorola, Inc. Low inductance semiconductor package
JP3013794B2 (en) * 1996-12-10 2000-02-28 富士電機株式会社 Semiconductor device

Also Published As

Publication number Publication date
JPS6184047A (en) 1986-04-28

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