JPH04147671A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to prevent the value of resistance of a highly resistive layer from decreasing at the time of high potential by causing an insulating film and conductor layer to intervene between the highly resistive layer and layer insulation film and by fixing the conductor layer to a low potential level. CONSTITUTION:In a memory cell, when L and H levels are written in connections P1 and P2 respectively, a first MOS transistorTr1 is placed in ON state because the H level is given to the gate G of the transitorTr1 via wiring l1 while the gate G and wiring l1 of the first MOS transistorTr1 reach the same potential as that of a DC power supply Vcc. Even if the DC power Vcc rises and the potential of a wiring polycrystalline silicon film 10 rises in company therewith, not only a second layer insulation silicon oxide film 11 but also a polycrystalline silicon film 17 fixed at a low potential level and silicon oxide film 18 intervene between a polycrystalline silicon film 13 for high resistance and the wiring polycrystalline silicon film 10 so that electrons can be prevented from collecting at the polycrystalline silicon film 13 for high resistance to prohibit the decrease of the value of resistance of the silicon film 13.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a method in which at least one conductor layer among a plurality of conductor layers formed on a semiconductor substrate via a glabellar isolation film is a high-resistance layer. The present invention relates to a semiconductor device in which a conductor layer for wiring which can be at a relatively high potential is disposed below the high resistance layer via a glabella separation film.

<Prior Art> As an example of a semiconductor device in which a wiring conductor layer that can have a relatively high potential is arranged below a high-resistance layer through an interlayer 1llIl as described above, there is a high-resistance load type static RAM ( This will be explained using SRAM).

In a typical high resistance load type static RAM, a gate electrode is formed in the first conductor layer, and a wiring region (low resistance region) and a high resistance region are formed in the second conductor layer. However, in recent years, with the progress of ultra-fine design, the number of conductor layers has increased to two
There is a transition from a 71-layer structure to a 3-layer structure. For example, a gate electrode is formed in the first layer, a low resistance wiring layer is formed in the second layer, and a high resistance layer is formed in the third layer.

Specifically, FIG. 4 shows the structure of a conventional high resistance load type static RAM. In the figure, 1 is a silicon substrate, 2 is a field silicon oxide film, 3 is a gate silicon oxide film, 4 is a polycrystalline silicon film for gate electrode, 5 is a source, 6 is a drain, and 7 is a silicon oxide film for first layer isolation. , 8 is a contact hole, 9 and 10 are polycrystalline silicon films for wiring, 11 is a silicon oxide film for second layer isolation, 12
a.

12b is a contact hole, 13 is a polycrystalline silicon film for high resistance, 14 is a silicon oxide film for third layer isolation, 15
1 is an aluminum wiring, and 16 is a passivation film.

The manufacturing process of such a high resistance load type static RAM will be briefly explained.

(2) A field silicon oxide film 2 for isolation is formed on the main surface of the silicon substrate 1 to a thickness of about 6,000 layers.

(2) A gate oxide silicon film 3 is formed to a thickness of approximately 200 nm by thermal oxidation of the silicon substrate 1.

■ Using CVD technology, a polycrystalline silicon film to be used as a gate electrode is deposited on a gate oxide silicon substrate to a thickness of approximately 4,000 Ω, and by thermally diffusing phosphorus into this film, a resistance of approximately 50 Ω is achieved.
A polycrystalline silicon film 4 for a gate electrode having a resistance value of approximately 1/2 is obtained.

■ After patterning the polycrystalline silicon film 4 for gate electrode and the gate silicon oxide film 3 to expose the main surface of the silicon substrate 1 using ordinary photolithography technology, the exposed portions are patterned using ion implantation technology. A source 5 and a drain 6 are formed by implanting impurities.

■ Using CVD technology, a first silicon oxide film 7 for interlayer isolation is formed on the field silicon oxide film 2, polycrystalline silicon film 4 for gate electrode, source 5, and drain 6 to a thickness of about 1,500 mm.
Formed with the thickness of a person.

■ Silicon oxide Wa for first layer separation using photo-etching technology
Finally, a contact hole 8 is formed.

■ Approximately 3,000 polycrystalline silicon films are made using CVD technology.
Polycrystalline silicon films 9 and 10 for wiring with a thickness of approximately 100 to 500 Ω/hole are obtained by depositing the polycrystalline silicon films 9 and 10 to a thickness of about 100 Ω/cm, and by ion-implanting As into the film.

■ Polycrystalline silicon film for wiring using photo-etching technology 9.
10 is patterned into a predetermined shape.

■ Polycrystalline silicon film for wiring using CVD technology 9.1
0, a second interlayer isolation silicon oxide film 11 is deposited about 150 m
Formed with a film thickness of 0.

[Phase] Contact holes 12a and 12b are formed in the second interlayer isolation silicon oxide film 11 by photolithography.

■ A polycrystalline silicon film 13 for high resistance is obtained by depositing a polycrystalline silicon film to a thickness of approximately 500 cm using CVD technology and implanting phosphorous into this film at a thickness of approximately 1×10'3/cm. .

■ Polycrystalline silicon film 1 for high resistance using photo-etching technology
3 is etched and patterned into a predetermined shape. The resistance value per piece of this high resistance polycrystalline silicon Y13 is 5
~IOTΩ (T=X10'), which is extremely high.

@ A third silicon oxide film 14 for interlayer isolation is formed on the polycrystalline silicon film 13 for high resistance. An opening is formed in this, an aluminum wiring 15 is formed, and finally a passivation film 16 is formed on the entire surface.

FIG. 5 shows the circuit configuration of a memory cell in a high resistance load type static RAM. Note that the memory cells shown in FIG. 5 (excluding MoS transistors Tr= and Tra) are composed of two sets of structures shown in FIG. 4.

In the figure, Tr+ and Try are first and second MOS transistors, 1. ．． 1. is the wiring, RNI is the first high resistance, RN
ffi is a second high resistance, T"ff, and Tr4 are MOS transistors for reading and writing data.

The first MOS transistor Tr, (or the second M
The gate G of the OS transistor T r t ) is connected to the polycrystalline silicon film 4 for gate electrode, the wiring p (or wiring 12) is connected to the polycrystalline silicon film 1110 for wiring, and the first high resistance R, , (or the second The high resistance RH corresponds to the high resistance polycrystalline silicon 813, respectively.

The operation of this memory cell will be briefly explained.

Now, hypothetically, "L" is written to the connection point P1 between the first high resistance R□1 and the drain D of the first MOS transistor Tr through the MOS transistor Tr3, and the second high resistance RM2 and the second Assume that "H" level is written to the connection point P2 between the drain D of the MOS transistor Tr2 through the MOS transistor Tr4.

In this case, the first MOS transistor T r + is
Arranged at the gate G&11. Since the “H” level is applied through
The second MOS transistor Trt is connected to the gate G by the wiring l,
Since the "L" level is applied through P!, it becomes OFF state, and the connection point P! is connected to the DC power supply Vcc via the second high resistance R++t, so it maintains the "H" level.

When the first MOS transistor Tr is in the ON state, the connection point P
1, when the "L" level is held at the "L" level, a current flows from the DC power supply Vcc to the line from the first high resistance R11l to the connection point P1 to the first MOS transistor Tr+ to the ground GND, and the current value is equal to the first It is determined by the resistance value of the high resistance RNI.

<Problems to be Solved by the Invention> Since the memory cells of the conventional static RAM are configured as described above, they have the following problems.

When the second MOS transistor Tr is in the OFF state,
The wiring 11 and the gate G of the first MOS transistor Tr have the same voltage as the DC power supply Vcc. That is,
The potential of the wiring polycrystalline silicon film (wiring conductor layer) 10 and the gate electrode polycrystalline silicon WI4 becomes Vcc.

When the DC power supply Vcc rises to 3 to 5 [V] and the potential of the wiring polycrystalline silicon film (wiring conductor layer) 10 rises, the second interlayer isolation silicon oxide film (interlayer bone 111) increases. 11 has a very thin film thickness of about 1,500 people,
Electrons are collected in the high resistance polycrystalline silicon film Wl (high resistance layer) 13 by static induction, and as a result, the resistance value of this high resistance polycrystalline silicon film (high resistance layer) 13 decreases.

The manner in which this resistance value decreases will be explained using the voltage-current characteristic diagram shown in FIG. In this characteristic diagram, the voltage is high resistance R+t+ (or R
t+z), and the current is the current flowing through that high resistance.

Characteristic a means that there is no wiring polycrystalline silicon film 10 that can have a relatively high potential under the high-resistance polycrystalline silicon film 13, and that the base of the high-resistance polycrystalline silicon film 13 is only a silicon oxide film. In this case, the characteristics are almost linear.

The characteristics show the case of the memory cell structure shown in FIG. 4 in which the polycrystalline silicon film 10 for wiring exists under the polycrystalline silicon film 13 for high resistance, and as described above, the DC power supply Vcc is
As the resistance value increases, the resistance value of the high resistance polycrystalline silicon film 13 decreases, and as a result, the current flowing through the high resistance polycrystalline silicon film 13 increases.

When a static RAM is backed up by a battery, the above-mentioned increase in current shortens the life of the backup pantry, resulting in a severe drawback that the period of memory backup becomes short.

In the above, in a static RAM memory cell,
Although we have pointed out the problem when the wiring polycrystalline silicon film 10 exists under the high-resistance polycrystalline silicon film 13 via the interlayer isolation silicon oxide film 11, similar problems can occur in static RAM, Comparisons are made not only when the high resistance layer and the wiring conductor layer are formed of polycrystalline silicon films, and the interlayer separation film is formed of silicon oxide film, but also when the interlayer separation film is provided below the high resistance layer. This applies to semiconductor devices in general in which a wiring conductor layer that can have a high potential is arranged.

The present invention has been devised to solve the above-mentioned problems, and is directed to a semiconductor in which a wiring conductor layer that can have a relatively high potential is arranged below a high-resistance layer via an interlayer separation film. It is an object of the present invention to prevent a decrease in the resistance value of a high resistance layer when a wiring conductor layer has a high potential in a device.

<Means for Solving the Problems> [+] A first semiconductor device according to the present invention has a wiring conductor layer that can be at a relatively high potential placed under a high-resistance layer via an interlayer separation film. In the semiconductor device, an insulating film and a conductive layer are interposed between the high resistance layer and the interlayer bone film, with the insulating film being in contact with the high resistance layer and the conductive layer being in contact with the interlayer separation film, and It is characterized in that the conductor layer is fixed at a low potential level.

[11] A second semiconductor device according to the present invention is characterized in that, in the first semiconductor device, the conductor layer is fixed to a ground level.

[nl] A third semiconductor device according to the present invention includes a pair of high-resistance layers, a pair of Mo3 transistors connected in series to each high-resistance layer, and a transistor on the opposite side of the connection point between each high-resistance layer and the Mo3 transistor. A high-resistance load type memory cell group comprising a wiring conductor layer connecting the gate electrode of a MOS transistor, and an interlayer isolation film interposed between the high-resistance layer and the wiring conductor layer. The static RAM is configured such that in each memory cell, an insulating film and a conductive layer are provided between a pair of high resistance layers and an interlayer bone III film, respectively, and the insulating film is in contact with the high resistance layer and the conductive layer is in contact with the high resistance layer. interlaminar bone S
It is characterized in that the pair of conductor layers are interposed in contact with the membrane, and the pair of conductor layers are fixed at a low potential level.

[TV] In the fourth semiconductor device according to the present invention, in the third semiconductor device (high resistance load type static RAM), each of the conductor layers is connected to a connection point between the high resistance layer and the Mo3 transistor. characterized by something.

<Function> [+] According to the first semiconductor device, the insulating film and the conductor layer are interposed between the high resistance layer and the interlayer separation film, and the conductor layer is fixed at a low potential level. Even if the wiring conductor layer under the separation membrane has a high potential, the presence of the conductor layer fixed at a -low potential level and the insulating film above it prevents electrons from gathering in the high resistance layer. Therefore, a decrease in the resistance value of this high resistance layer is prevented.

[■] According to the second semiconductor device, the low potential level that fixes the conductor layer in the first semiconductor device is used as the ground level, so the potential of the wiring conductor layer under the interlayer separation film is quite high. Even if this happens, it does not affect the resistance value of the high resistance layer at all.

[I[1] According to the third semiconductor device (static RAM), by having the same configuration as the first semiconductor device, when backing up the static RAM, the high resistance layer connected to the ON side Mo3 transistor It is possible to suppress an increase in the flowing current, and it is possible to lengthen the memory bank up time using the battery.

[]V] According to the fourth semiconductor device (static RAM), in the third semiconductor device, the conductor layer is connected to the connection point of the high resistance layer and the MoS transistor;
A low potential level can be applied to the conductor layer inside the memory cell, and the structure is simplified compared to the case where a low potential level is applied from the outside.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

Figure 1 shows a cross-sectional structure of a high resistance load type static RAM according to a first embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a field silicon oxide film, 3 is a gate oxide silicon film, 4 is a polycrystalline silicon film for the first layer gate electrode, 5 is a source, 6 is a drain, and 7 is a first interlayer Isolation silicon oxide film, 8 is a contact hole, 9
．． 10 is a polycrystalline silicon film for second layer wiring (conductor layer for wiring), and 11 is a silicon oxide film for second layer isolation (interlayer isolation film), which are basically the same as the conventional example shown in FIG. is the same as

The configuration of this embodiment that differs from the conventional example is shown in Figs. 1 and 4.
As can be seen from a comparison with the figure, a polycrystalline silicon film (conductor layer ) 17 and silicon oxide film (
An insulating film 18 is interposed therebetween.

The manufacturing procedure of a static RAM having such a structure will be briefly described below.

Note that the manufacturing process up to the second interlayer isolation silicon oxide film 11 is the same as described in the conventional example, so a description thereof will be omitted here.

■ First, on the second interlayer isolation silicon oxide film 11,
A polycrystalline silicon film is formed over the entire surface to a thickness of approximately 2000 nm, and after implanting As into this using ion implantation technology, the upper part of the wiring polycrystalline silicon film 10 is covered in this impurity-doped polycrystalline silicon film. A polycrystalline silicon film 17 is obtained by patterning using photolithography so that only the region remains (see FIG. 2, 18+).

■ A silicon oxide film 18 with a thickness of about 200 mm is entirely coated on the polycrystalline silicon film 17 and the second interlayer isolation silicon oxide film 11.
It is formed with a film thickness of 0.0 mm [see Fig. 2 (bl)].

■ By patterning the silicon oxide film 18 and the second interlayer isolation silicon oxide film 11 using photolithography, contact holes 12a and 12b are formed for the wiring polycrystalline silicon film 9 [see Fig. 2 (C1)]. ].

■ Using CVD technology, a polycrystalline silicon film was deposited over the entire surface to a thickness of approximately 500 mm, and phosphorus was ion-implanted to a thickness of about 1 x 103/cm to form a high-resistance polycrystalline silicon film, which was photographed. By patterning using etching technology, the resistance value per wire is 5~LOTΩ (T=X 1
A high resistance polycrystalline silicon film 13 having a resistance of about 0") is obtained (see FIG. 2, 18+). Then, a second interlayer isolation silicon oxide film 14 is formed on the high resistance polycrystalline silicon film 13, as is well known. , an aluminum wiring 15, and a pansivation film 16 to obtain the structure shown in FIG.

Note that the polycrystalline silicon film 17 is fixed at a low potential level (preferably ground level) from the outside.

If these two sets of structures are represented as a circuit, they will be as shown in FIG. 5, and the operation of the structure of this embodiment will be as follows.

Now, suppose that in the memory cell shown in FIG.
Suppose that "L" level is written to the connection point P, and "H" level is written to the connection point P, then the first MOS transistor Tr is arranged at the gate (G) is 7! Since “H” level is applied through I, it becomes ON state,
A current flows from the DC power supply Vcc to the line from the first high resistance RHI, the connection point, the first OS transistor Tr+, and the ground GND.

At this time, the gate G of the first MOS transistor Tr
And distribution Fa 7! I has the same potential as the DC power supply Vcc. That is, the potential of the gate electrode polycrystalline silicon film 4 and the wiring polycrystalline silicon film #10 becomes Vcc.

Even if the DC power supply Vcc rises to 3 to 5 [■] and the potential of the wiring polycrystalline silicon film 10 rises, the wiring polycrystalline silicon film 10 and the high resistance polycrystalline silicon l
113, there is a silicon oxide film 1 for second layer isolation.
1, but also a polycrystalline silicon film 17 and a silicon oxide film 18 that are fixed at a low potential level.
It is possible to prevent electrons from collecting in the high resistance polycrystalline silicon film 13 due to electrostatic induction from the wiring polycrystalline silicon film 10 whose potential has increased, and the resistance 41. prevent decline.

Therefore, when static RAM is banked up,
First MOS transistor Tr1 in ON state
Further, an increase in the current flowing through the high resistance polycrystalline silicon film 13, which is the first high resistance RMI connected thereto, can be suppressed. In the range of 3 to 5 [V] applied to the DC power supply VCC during actual use, the voltage-current characteristic becomes similar to the linear characteristic a in Figure 6, which suppresses the current consumption necessary for the memory bank amplifier. , the backup time can be extended.

11th Saturday FIG. 3 shows a second embodiment of the invention.

In FIG. 3, the same reference numerals as those shown in FIG. 1 according to the first embodiment refer to the same parts in this embodiment as well, and their mutual relationships and manufacturing procedures are explained. Since it is the same as the first embodiment, the explanation will be omitted.

This embodiment has a different configuration from the first embodiment in that the polycrystalline silicon film ( A conductor layer) 17 is interposed therebetween. In other words, the first high resistance R in FIG.
MI and the drain D of the first MOS transistor Tr+
connection point P, the second high resistance RHt, and the second MOS
At the connection point P2 with the drain D of the transistor Try,
This means that the polycrystalline silicon film 17 is connected. Of course, the polycrystalline silicon film 17 is separated between the first MOS transistor Tr and the second MOS transistor Tr.

When the first MOS transistor Tr, (or the second MOS transistor Tr,) is turned on, a current flows through the first high resistance RH1 (or the second high resistance R9□), but the MOS transistor Since the source S of Tr, (or Trz) is grounded to the ground GND, the potential of the connection point P, (or P2) is approximately at the ground level, and the same effect as in the first embodiment can be obtained.

Further, since a low potential level is applied to the polycrystalline silicon film 17 inside the memory cell rather than from outside, the structure can be further simplified.

Although each of the above embodiments was related to a static RAM, the structure of the present invention can be applied to any semiconductor device having a high resistance layer of about 109Ω or more, so it is possible to reduce the resistance value of the high resistance layer. It is possible to alleviate this problem and prevent an increase in current consumption.

<Effects of the Invention> N) According to the first semiconductor device of the present invention, electrons gather in the high resistance layer due to the high potential of the wiring conductor layer under the interlayer separation film. A decrease in the resistance value can be prevented by the presence of a conductive layer and an insulating film interposed between the high resistance layer and the interlayer portion HM and fixed at a low potential level.

CI+) According to the second semiconductor device of the present invention, the low potential level applied to the conductor layer is set as the ground level, so even if the potential of the wiring conductor layer under the interlayer isolation film becomes considerably high, There is no need to affect the resistance value of the resistance layer at all.

(I [I] According to the third semiconductor device (static RAM) according to the present invention, it is possible to suppress the increase in the current flowing through the high resistance layer connected to the MOS transistor on the side that is turned on during memory bank up. This makes it possible to suppress the current consumption required for memory bank up and lengthen the bank up time.

(rV) According to the fourth semiconductor device (static RAM) according to the present invention, a low potential level is applied to the conductor layer inside the memory cell by connecting the conductor layer to the connection point of the high resistance layer and the MOS transistor. Therefore, the structure can be simplified compared to the case where a low potential level is applied externally.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 relate to a first embodiment of the present invention.
The figure is a cross-sectional structural diagram of a semiconductor device (static RAM).
FIG. 2 ta+ to fd+ are process diagrams showing the manufacturing process. FIG. 3 is a cross-sectional structural diagram of a semiconductor device (static RAM) according to a second embodiment of the present invention. FIG. 4 shows a semiconductor device N (static RAM) according to a conventional example.
) is a cross-sectional structural diagram of. Note that FIGS. 5 and 6 are used in common to explain the conventional example and the present invention, and
FIG. 5 is a circuit configuration diagram of a memory cell in a high resistance load type static RAM, and FIG. 6 is a voltage-current characteristic diagram of a high resistance polycrystalline silicon film. 10... Polycrystalline silicon film for wiring (conductor layer for wiring),
11... Silicon oxide film for second interlayer isolation (interlayer isolation film) 13... Polycrystalline silicon film for high resistance (high resistance layer),
17... Polycrystalline silicon film, ]8... Silicon oxide M (insulating film).

Claims (4)

[Claims] (1) A semiconductor device in which a wiring conductor layer that can have a relatively high potential is arranged below a high-resistance layer via an interlayer separation film, wherein between the high-resistance layer and the interlayer separation film, 1. A semiconductor device comprising an insulating film and a conductor layer interposed in such a manner that the insulating film is in contact with a high resistance layer and the conductor layer is in contact with an interlayer separation film, and the conductor layer is fixed at a low potential level. (2) The semiconductor device according to claim 1, wherein the conductor layer is fixed at a ground level. (3) For wiring connecting a pair of high-resistance layers, a pair of MOS transistors connected in series to each high-resistance layer, and the gate electrode of the MOS transistor on the opposite side of the connection point of each high-resistance layer/MOS transistor. A semiconductor device constituting a high-resistance load type static RAM comprising a memory cell group having a conductor layer and an interlayer isolation film interposed between the high-resistance layer and the wiring conductor layer, In each of the memory cells, an insulating film and a conductive layer are interposed between the pair of high resistance layers and the interlayer isolation film, respectively, with the insulating film being in contact with the high resistance layer and the conductor layer being in contact with the interlayer isolation film, and A semiconductor device characterized in that the pair of conductor layers are fixed at a low potential level. (4) The semiconductor device according to claim (3), wherein each of the conductor layers is connected to a connection point between the high resistance layer and the MOS transistor.