JP3144406B2 - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JP3144406B2
JP3144406B2 JP33881498A JP33881498A JP3144406B2 JP 3144406 B2 JP3144406 B2 JP 3144406B2 JP 33881498 A JP33881498 A JP 33881498A JP 33881498 A JP33881498 A JP 33881498A JP 3144406 B2 JP3144406 B2 JP 3144406B2
Authority
JP
Japan
Prior art keywords
wiring
diffusion layer
layers
semiconductor memory
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33881498A
Other languages
Japanese (ja)
Other versions
JP2000164821A (en
Inventor
貴美 永田
哲史 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33881498A priority Critical patent/JP3144406B2/en
Priority to US09/447,214 priority patent/US6359297B1/en
Publication of JP2000164821A publication Critical patent/JP2000164821A/en
Application granted granted Critical
Publication of JP3144406B2 publication Critical patent/JP3144406B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体記憶装置に
関し、特に、誤動作しない半導体記憶装置に関する。The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which does not malfunction.

【０００２】[0002]

【従来の技術】一般に、半導体記憶装置では、セルブロ
ックに隣接してグランド配線（以下、ＧＮＤ配線とす
る）を設ける。これは全てのセルでＧＮＤレベルを安定
にするためである。このＧＮＤ配線にはセルやＶｃｃ配
線が隣接している。2. Description of the Related Art Generally, in a semiconductor memory device, a ground wiring (hereinafter referred to as a GND wiring) is provided adjacent to a cell block. This is to stabilize the GND level in all cells. A cell and a Vcc wiring are adjacent to this GND wiring.

【０００３】図３は、従来の半導体記憶装置のセルブロ
ック端を示す断面図である。ＧＮＤ配線１２と、第１お
よび第２のＶｃｃ配線２３，２４とが、セルブロックに
隣接している。一般的に、温度約８５℃、湿度約７０％
の環境で半導体装置を使用すると、極微量の水分の影響
で陽イオンが発生し、ＧＮＤ配線に引きつけられる。Ｇ
ＮＤ配線にひきつけられた陽イオンは、ＧＮＤ配線また
はＧＮＤ配線に隣接したセルへ拡散していき、ＧＮＤ配
線またはセルの拡散層にチャージがたまり、その結果、
ＧＮＤ配線とセルとの間に電流が流れて誤動作をする。FIG. 3 is a sectional view showing a cell block end of a conventional semiconductor memory device. The GND wiring 12 and the first and second Vcc wirings 23 and 24 are adjacent to the cell block. Generally, temperature about 85 ° C, humidity about 70%
When the semiconductor device is used in the environment described above, cations are generated under the influence of a very small amount of water, and are attracted to the GND wiring. G
The cations attracted to the ND wiring diffuse into the GND wiring or a cell adjacent to the GND wiring, and charge is accumulated in the GND wiring or a diffusion layer of the cell.
A current flows between the GND wiring and the cell, causing a malfunction.

【０００４】[0004]

【発明が解決しようとする課題】上述したように、従来
の半導体記憶装置では、ＧＮＤ配線とセルとの間に電流
が流れて誤動作するという問題があった。As described above, the conventional semiconductor memory device has a problem that a current flows between the GND wiring and the cell, causing a malfunction.

【０００５】そこで、本発明の目的は、上記問題を解決
するために、ＧＮＤ配線とセルとの間に電流が流れて誤
動作することがない半導体記憶装置を提供することにあ
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device in which a current does not flow between a GND wiring and a cell and malfunctions in order to solve the above problem.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体記憶装置は、グランド配線がセルブ
ロックに隣接して配置されている半導体記憶装置におい
て、グランド配線に隣接してかつ対向して配置された第
１および第２の配線層と、第１および第２の配線層の下
方にそれぞれ設けられた第１および第２の拡散層とを備
えたことを特徴とする。In order to achieve the above object, a semiconductor memory device according to the present invention is a semiconductor memory device in which a ground line is arranged adjacent to a cell block. It is characterized by comprising: first and second wiring layers arranged to face each other; and first and second diffusion layers provided below the first and second wiring layers, respectively.

【０００７】また、第１および第２の配線層の電位と、
第１および第２の拡散層の電位とは、グランド配線より
高いのが好ましい。In addition, the potentials of the first and second wiring layers are
It is preferable that the potentials of the first and second diffusion layers are higher than the ground wiring.

【０００８】さらに、第１および第２の配線層と、第１
および第２の拡散層とは、同一の電位レベルであるのが
好ましい。Further, the first and second wiring layers,
And the second diffusion layer are preferably at the same potential level.

【０００９】またさらに、第１および第２の配線層と、
第１および第２の拡散層とは、異なる電位レベルである
のが好ましい。Further, the first and second wiring layers,
Preferably, the potential levels are different from those of the first and second diffusion layers.

【００１０】また、グランド配線を挟むセルブロックの
セル拡散層として配置された第３および第４の拡散層を
備えるのが好ましい。It is preferable that the semiconductor device further includes third and fourth diffusion layers arranged as cell diffusion layers of a cell block sandwiching the ground wiring.

【００１１】さらに、第１および第２の配線層と、第１
および第２の拡散層とは、グランド配線と第３および第
４の拡散層との間に配置されるのが好ましい。Further, the first and second wiring layers,
The second diffusion layer is preferably disposed between the ground wiring and the third and fourth diffusion layers.

【００１２】[0012]

【発明の実施の形態】次に、図面を参照して、本発明の
実施例について詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described in detail with reference to the drawings.

【００１３】図１は、本発明の半導体記憶装置の実施例
のセルブロック端を示す平面図である。第１のグランド
（ＧＮＤ）配線１１，第１のＶｃｃ配線２１，第２のＶ
ｃｃ配線２２は、セルブロックに隣接している。FIG. 1 is a plan view showing a cell block end of an embodiment of a semiconductor memory device according to the present invention. First ground (GND) wiring 11, first Vcc wiring 21, second Vcc wiring
The cc wiring 22 is adjacent to the cell block.

【００１４】また、図２は、図１のＡ−Ａ’における断
面図である。第１のＶｃｃ配線２１，第２のＶｃｃ配線
２２に対応して、第１および第２のＶｃｃ配線２１，２
２と同一または異なる正の電位の拡散層である第１の拡
散層３１，第２の拡散層３２が配置されている。また、
第１の拡散層３１，第２の拡散層３２に対応してセルブ
ロック端のセルの拡散層である第３の拡散層４１，第４
の拡散層４２が配置されている。第１および第２の拡散
層３１，３２は、第１および第２のＶｃｃ配線２１，２
２の下方にあり、第１および第２のＶｃｃ配線２１，２
２と第１および第２の拡散層３１，３２とは、第１のＧ
ＮＤ配線１１とセルブロック内拡散層である第３および
第４の拡散層４１，４２との間に配置する。このよう
に、ＧＮＤ配線とＶｃｃ配線と正の電位の拡散層とを配
置することにより、発生した陽イオンがＧＮＤ配線にひ
きつけらても、Ｖｃｃまたは正の電界によりセル部へ拡
散していくことがなく不良が発生しない。また、Ｖｃｃ
または正の電界により、ＧＮＤ配線へ陽イオンがひきつ
けられにくくなる。FIG. 2 is a sectional view taken along the line AA 'of FIG. First and second Vcc wirings 21 and 22 correspond to first Vcc wiring 21 and second Vcc wiring 22, respectively.
2, a first diffusion layer 31 and a second diffusion layer 32, which are diffusion layers having the same or different positive potentials. Also,
Corresponding to the first diffusion layer 31 and the second diffusion layer 32, the third diffusion layer 41 and the fourth
Are provided. The first and second diffusion layers 31 and 32 form first and second Vcc wirings 21 and
2 and the first and second Vcc wirings 21 and
2 and the first and second diffusion layers 31 and 32
It is arranged between the ND wiring 11 and the third and fourth diffusion layers 41 and 42 which are diffusion layers in the cell block. By arranging the GND wiring, the Vcc wiring, and the diffusion layer having a positive potential in this manner, even if the generated cations are attracted to the GND wiring, they are diffused into the cell portion by Vcc or a positive electric field. No defects occur. Also, Vcc
Alternatively, a positive electric field makes it difficult for cations to be attracted to the GND wiring.

【００１５】以上説明したように、本発明は、半導体記
憶装置において、チップ内に発生する陽イオンがセル部
に達しないような導電層のレイアウトに関し、セルブロ
ック間に素子分離酸化膜を挟んでセルブロック毎にＶｃ
ｃ以下の正電位を有する拡散層を配置し、拡散層上方に
はＶｃｃ配線２１，２２を走らせ、その間にＧＮＤ配線
１１を配置する。このレイアウトにより陽イオンの外部
からの侵入を防ぎ、ＧＮＤに引かれた陽イオンがあって
もそのイオンは拡散層によりセル部への侵入を防ぐこと
ができる。As described above, the present invention relates to a layout of a conductive layer in a semiconductor memory device in which cations generated in a chip do not reach a cell portion, with an element isolation oxide film interposed between cell blocks. Vc for each cell block
A diffusion layer having a positive potential equal to or lower than c is disposed, Vcc wirings 21 and 22 are run above the diffusion layer, and a GND wiring 11 is disposed therebetween. With this layout, cations can be prevented from invading from the outside, and even if there are cations attracted to GND, the ions can be prevented from entering the cell portion by the diffusion layer.

【００１６】[0016]

【発明の効果】本発明では、ＧＮＤ配線とＶｃｃ配線と
正の電位の拡散層とを配置することにより、発生した陽
イオンがＧＮＤ配線にひきつけらても、Ｖｃｃまたは正
の電界によりセル部へ拡散していくことがなく不良が発
生しないという効果を奏する。According to the present invention, by disposing the GND wiring, the Vcc wiring, and the diffusion layer having a positive potential, even if generated cations are attracted to the GND wiring, the cell section is applied to the cell by Vcc or a positive electric field. This has the effect of preventing defects from being diffused.

【００１７】また、Ｖｃｃまたは正の電界により、ＧＮ
Ｄ配線へ陽イオンがひきつけられにくくなるという効果
を奏する。Further, GN is generated by Vcc or a positive electric field.
This has the effect of making it difficult for cations to be attracted to the D wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置のセルブロック端を示す平
面図である。FIG. 1 is a plan view showing a cell block end of a semiconductor device of the present invention.

【図２】図１のＡ−Ａ’断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.

【図３】従来の半導体記憶装置のセルブロック端を示す
断面図である。FIG. 3 is a cross-sectional view showing a cell block end of a conventional semiconductor memory device.

【符号の説明】[Explanation of symbols]

１１ ＧＮＤ配線 １２ ＧＮＤ配線（従来例） ２１ 第１のＶｃｃ配線 ２２ 第２のＶｃｃ配線 ２３ 第１のＶｃｃ配線（従来例） ２４ 第２のＶｃｃ配線（従来例） ３１ 第１の拡散層 ３２ 第２の拡散層 ４１ 第３の拡散層 ４２ 第４の拡散層 DESCRIPTION OF SYMBOLS 11 GND wiring 12 GND wiring (conventional example) 21 1st Vcc wiring 22 2nd Vcc wiring 23 1st Vcc wiring (conventional example) 24 2nd Vcc wiring (conventional example) 31 1st diffusion layer 32nd 2nd diffusion layer 41 3rd diffusion layer 42 4th diffusion layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/10 H01L 21/3205 H01L 21/768 H01L 21/82 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 27/10 H01L 21/3205 H01L 21/768 H01L 21/82

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】グランド配線がセルブロックに隣接して配
置されている半導体記憶装置において、 前記グランド配線に隣接してかつ対向して配置された第
１および第２の配線層と、 前記第１および第２の配線層の下方にそれぞれ設けられ
た第１および第２の拡散層と、 を備えたことを特徴とする半導体記憶装置。1. A semiconductor memory device in which a ground wiring is arranged adjacent to a cell block, wherein the first and second wiring layers are arranged adjacent to and opposed to the ground wiring; And a first and a second diffusion layer provided below the second wiring layer, respectively. 【請求項２】前記第１および第２の配線層の電位と、前
記第１および第２の拡散層の電位とは、前記グランド配
線より高いことを特徴とする、請求項１に記載の半導体
記憶装置。2. The semiconductor according to claim 1, wherein a potential of said first and second wiring layers and a potential of said first and second diffusion layers are higher than said ground wiring. Storage device. 【請求項３】前記第１および第２の配線層と、前記第１
および第２の拡散層とは、同一の電位レベルであること
を特徴とする、請求項２に記載の半導体記憶装置。3. The first and second wiring layers and the first and second wiring layers.
3. The semiconductor memory device according to claim 2, wherein said second diffusion layer and said second diffusion layer have the same potential level. 【請求項４】前記第１および第２の配線層と、前記第１
および第２の拡散層とは、異なる電位レベルであること
を特徴とする、請求項２に記載の半導体記憶装置。4. The first and second wiring layers and the first and second wiring layers.
3. The semiconductor memory device according to claim 2, wherein said second diffusion layer and said second diffusion layer have different potential levels. 【請求項５】前記グランド配線を挟むセルブロックのセ
ル拡散層として配置された第３および第４の拡散層を備
えたことを特徴とする、請求項２〜４のいずれかに記載
の半導体記憶装置。5. The semiconductor memory according to claim 2, further comprising third and fourth diffusion layers arranged as cell diffusion layers of a cell block sandwiching said ground wiring. apparatus. 【請求項６】前記第１および第２の配線層と、前記第１
および第２の拡散層とは、前記グランド配線と前記第３
および第４の拡散層との間に配置されたことを特徴とす
る、請求項５に記載の半導体記憶装置。6. The first and second wiring layers and the first and second wiring layers.
And the second diffusion layer are the same as the ground wiring and the third diffusion layer.
The semiconductor memory device according to claim 5, wherein the semiconductor memory device is disposed between the semiconductor memory device and a fourth diffusion layer.
JP33881498A 1998-11-30 1998-11-30 Semiconductor storage device Expired - Fee Related JP3144406B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP33881498A JP3144406B2 (en) 1998-11-30 1998-11-30 Semiconductor storage device
US09/447,214 US6359297B1 (en) 1998-11-30 1999-11-23 Semiconductor device with movement of positive ion prevented

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33881498A JP3144406B2 (en) 1998-11-30 1998-11-30 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JP2000164821A JP2000164821A (en) 2000-06-16
JP3144406B2 true JP3144406B2 (en) 2001-03-12

Family

ID=18321712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33881498A Expired - Fee Related JP3144406B2 (en) 1998-11-30 1998-11-30 Semiconductor storage device

Country Status (2)

Country Link
US (1) US6359297B1 (en)
JP (1) JP3144406B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6923314B2 (en) * 2002-09-20 2005-08-02 Illinois Tool Works Inc. Banded container package with opening feature

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228753A (en) 1983-06-10 1984-12-22 Hitachi Ltd Semiconductor device
JPH04162660A (en) 1990-10-26 1992-06-08 Nec Corp Semiconductor device
JP3596830B2 (en) * 1995-11-27 2004-12-02 株式会社ルネサステクノロジ Input protection circuit for semiconductor device
KR100230426B1 (en) * 1996-06-29 1999-11-15 윤종용 Static random access memory device with improved integrated ratio

Also Published As

Publication number Publication date
JP2000164821A (en) 2000-06-16
US6359297B1 (en) 2002-03-19

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