JPH04145645A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPH04145645A JPH04145645A JP26985690A JP26985690A JPH04145645A JP H04145645 A JPH04145645 A JP H04145645A JP 26985690 A JP26985690 A JP 26985690A JP 26985690 A JP26985690 A JP 26985690A JP H04145645 A JPH04145645 A JP H04145645A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin sealed
- resin
- semiconductor device
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 24
- 229920005989 resin Polymers 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000004020 conductor Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 description 12
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
従来の樹脂封止型半導体装置では、たとえばQ F P
(Quad Flat Package)でのプリン
ト基板実装では、近年自動化が進み、自動実装にて行っ
ているのが通常である。In conventional resin-sealed semiconductor devices, for example, Q F P
(Quad Flat Package) Printed circuit board mounting has become increasingly automated in recent years, and is usually carried out automatically.
一般的に自動実装時の半導体装置実装方法は、第4図に
示すように、Aビン6及びBビン7のプリント基板接触
面A、B、C,D点を表面認識(二値画像)し樹脂封止
中心点3を見い出し、この中心点をもとにプリント基板
に精度高く実装し、半田付するのが通常であった。Generally, the semiconductor device mounting method during automatic mounting involves surface recognition (binary image) of points A, B, C, and D on the printed circuit board contact surfaces of the A bin 6 and B bin 7, as shown in Figure 4. It has been usual to find the center point 3 of resin sealing, and based on this center point, mount it on a printed circuit board with high precision and solder it.
上記した従来の半導体装置の実装位置認識方法は外部導
出リード先端部であるプリント基板接触面5を使用する
為、たとえば外部導出リード先端部がねじれ1曲り等変
形したままの状態で認識した場合、樹脂封止中心点位置
出しがずれてしまい、プリント基板の正常な位置に実装
されない不具合が発生してしまう。The conventional method for recognizing the mounting position of a semiconductor device described above uses the printed circuit board contact surface 5, which is the tip of the external lead. The center point of the resin sealing will be misaligned, resulting in a problem that the printed circuit board will not be mounted at the correct position.
その結果、外部導出リード先端であるプリント基板接触
面とプリント基板バット部との位置ずれが生じ半田付不
良又は、再実装による工数増等の欠点がある。As a result, there is a misalignment between the printed circuit board contact surface, which is the tip of the external lead, and the printed circuit board butt, resulting in disadvantages such as poor soldering and increased man-hours due to remounting.
本発明の目的は、精度の高い樹脂封止中心点を得ること
が可能な樹脂封止型半導体装置を提供することにある。An object of the present invention is to provide a resin-sealed semiconductor device that can obtain a highly accurate resin-sealed center point.
本発明の樹脂封止型半導体装置は、外部導出リードが四
方向に所定のピッチで導出され、前言己外部導出リード
先端部が実装基板上の導体層に平行接触している樹脂封
止型半導体装置において、対向す−る辺の対角線上に位
置する少なくとも2つの前記外部導出リード上面にある
上金型樹脂止部に内部導出リード表面まで達する開口部
を設けたことを特徴とする。The resin-sealed semiconductor device of the present invention is a resin-sealed semiconductor device in which external leads are led out at a predetermined pitch in four directions, and the tips of the external leads are in parallel contact with a conductor layer on a mounting board. The device is characterized in that the upper mold resin stopper on the upper surface of at least two of the external lead-out leads located diagonally on opposite sides is provided with an opening that reaches the surface of the inner lead-out lead.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(c)はそれぞれ本発明の一実施例を示
す正面図、平面図、側面図、第2図は第1図に示すA部
の部分拡大図である。このチップは、半導体素子が固着
マウントされる素子搭載部と、素子搭載部の近傍まで延
びてくる複数のリード部と、リード先端部と半導体素子
とをワイヤーボンディングして半導体素子を含む主要部
分を上下モールド金型による樹脂封止して構成されてい
る。外部導出リード1は四方向に所定のピッチで導出さ
れ、外部導出リード先端部が実装基板上の導体層に平行
接触して電気伝導を保つ様に加工しである。FIGS. 1(a) to (c) are a front view, a plan view, and a side view showing one embodiment of the present invention, respectively, and FIG. 2 is a partially enlarged view of section A shown in FIG. 1. This chip consists of an element mounting part on which the semiconductor element is fixedly mounted, a plurality of lead parts extending to the vicinity of the element mounting part, and a main part including the semiconductor element by wire bonding the lead tips and the semiconductor element. It is constructed by resin sealing using upper and lower molds. The external lead-out leads 1 are led out at a predetermined pitch in four directions, and are processed so that the tips of the external lead-out leads come into parallel contact with the conductor layer on the mounting board to maintain electrical conduction.
このようなチップにおいて、対向する辺の対角線上に位
置する点の樹脂封止界面8から導出されるリード例えば
Aビン6とBビン7の上金型樹脂封止部9に幅1.0m
m、長さ1.0mm程度の内部導出リード部分11にま
で達した開口部4を設けている。In such a chip, a lead with a width of 1.0 m is attached to the upper mold resin sealing portion 9 of the A-bin 6 and the B-bin 7, which are led out from the resin-sealing interface 8 at points located diagonally on the opposite sides.
An opening 4 reaching an internal lead-out lead portion 11 having a length of about 1.0 mm and a length of about 1.0 mm is provided.
このような構造にすることにより、内部導出リード11
の表面点A、B、C,D点を用いて二値画像による表面
認識することにより、リード部のねじれ等の影響がなく
なるため、精度の高い樹脂封止中心点3を得ることが出
来る。By adopting such a structure, the internal lead-out lead 11
By performing surface recognition using a binary image using the surface points A, B, C, and D, the influence of twisting of the lead portion, etc. is eliminated, so that it is possible to obtain the resin-sealing center point 3 with high accuracy.
第3図(a)〜(c)はそれぞれ本発明の第2の実施例
を示す正面図、平面図、側面図である。FIGS. 3(a) to 3(c) are a front view, a plan view, and a side view, respectively, showing a second embodiment of the present invention.
二対の対向する辺の対角線上に位置する点の樹脂封止界
面8から導出されるリード1の上金型樹脂封止部9に幅
1.Omm長さ1.0mm程度の開口部4を設け、計4
点にて二値画像による表面認識する。The upper mold resin sealing portion 9 of the lead 1, which is led out from the resin sealing interface 8 at a point located on the diagonal of two pairs of opposing sides, has a width of 1. An opening 4 with a length of about 1.0 mm is provided, and a total of 4 openings are provided.
Surface recognition using binary images at points.
本実施例では、4点認識である為、より精度の高い樹脂
封止中心点3を得ることが出来る。In this embodiment, since four points are recognized, it is possible to obtain the resin sealing center point 3 with higher accuracy.
以上説明した実施例において、開口部のサイズを幅1.
Qmm、長さ1.0mmとして説明したが、本発明では
通常のビン幅として用いられる0、5mmから1.0m
m程度のサイズであれば、上述した同様の効果が得られ
る。又、開口部の幅と長さが等しい必要はなく、2つの
値が異っていても、中心点を求める精度には影響しない
。In the embodiment described above, the size of the opening is set to 1.
Qmm, the length was explained as 1.0mm, but in the present invention, the width is 1.0m from 0.5mm, which is used as a normal bin width.
If the size is about m, the same effect as described above can be obtained. Further, the width and length of the opening need not be equal, and even if the two values are different, the accuracy of determining the center point will not be affected.
以上説明したように本発明は、外部導出リードが四方向
に所定のピッチで導出され、かつ外部導出リード先端部
が実装基板上の導体層に平行接触して電気伝導を保つ様
に加工しである樹脂封止型半導体装置において、対向す
る辺の対角線上に位置する点の樹脂封止界面から導出さ
れるリードの上金型樹脂止部に内部導出リード表面まで
たつする開口部を設け、この開口部を二値画像による表
面認識させることにより精度の高い樹脂封止中心点を得
ることが出来る。As explained above, in the present invention, the external leads are led out at a predetermined pitch in four directions, and the tips of the external lead leads are processed in parallel to the conductor layer on the mounting board to maintain electrical conduction. In a certain resin-sealed semiconductor device, an opening extending to the surface of the inner lead-out lead is provided in the upper mold resin stopper of the lead led out from the resin-sealed interface at a point located on the diagonal of the opposing sides. By performing surface recognition of the opening using a binary image, a highly accurate resin sealing center point can be obtained.
これにより、プリント基板上に配置しであるマウントパ
ッドに位置ずれのない精度良い自動実装が可能になる効
果がある。This has the effect of enabling highly accurate automatic mounting without misalignment of the mount pads arranged on the printed circuit board.
第1図(a)〜(c)はそれぞれ本発明の一実施例を示
す樹脂封止型半導体装置の正面図、平面図及び側面図、
第2図は、第1図に示すA部の拡大投影図、第3図(a
)〜(c)は、それぞれ本発明の第2の実施例を示す正
面図、平面図及び側面図、第4図(a)〜(c)はそれ
ぞれ従来の樹脂封止型半導体装置の正面図、平面図及び
側面図である。
1・・・外部導出リード、2・・・樹脂封止、3・・・
樹脂封止中心点、4・・・樹脂封止開口部、5・・・基
板接触面、6・・・Aピン、7・・・Bビン、8・・・
樹脂封止界面、9・・・上金型樹脂封止部、10・・・
下金型樹脂封止部、11・・・内部導出リード。FIGS. 1(a) to 1(c) are a front view, a top view, and a side view of a resin-sealed semiconductor device showing an embodiment of the present invention, respectively;
Figure 2 is an enlarged projected view of part A shown in Figure 1, and Figure 3 (a
) to (c) are respectively a front view, a plan view, and a side view showing the second embodiment of the present invention, and FIGS. 4(a) to (c) are front views of a conventional resin-sealed semiconductor device, respectively. , a plan view and a side view. 1...External lead-out lead, 2...Resin sealing, 3...
Resin sealing center point, 4... Resin sealing opening, 5... Board contact surface, 6... A pin, 7... B bottle, 8...
Resin sealing interface, 9... Upper mold resin sealing part, 10...
Lower mold resin sealing part, 11...internal lead-out lead.
Claims (1)
、前記外部導出リード先端部が実装基板上の導体層に平
行接触している樹脂封止型半導体装置において、対向す
る辺の対角線上に位置する少なくとも2つの前記外部導
出リード上面にある上金型樹脂止部に内部導出リード表
面まで達する開口部を設けたことを特徴とする樹脂封止
型半導体装置。 2、前記開口部の幅及び長さがそれぞれ0.5mm以上
1.0mm以内としたことを特徴とする請求項1記載の
樹脂封止型半導体装置。[Claims] 1. In a resin-sealed semiconductor device in which external leads are led out at a predetermined pitch in four directions, and the tips of the external leads are in parallel contact with a conductor layer on a mounting board, A resin-sealed semiconductor device characterized in that an upper mold resin stopper on the upper surface of at least two external lead-out leads located on a diagonal line of a side thereof is provided with an opening that reaches a surface of the inner lead-out lead. 2. The resin-sealed semiconductor device according to claim 1, wherein the width and length of the opening are each 0.5 mm or more and 1.0 mm or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26985690A JPH04145645A (en) | 1990-10-08 | 1990-10-08 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26985690A JPH04145645A (en) | 1990-10-08 | 1990-10-08 | Resin sealed type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04145645A true JPH04145645A (en) | 1992-05-19 |
Family
ID=17478154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26985690A Pending JPH04145645A (en) | 1990-10-08 | 1990-10-08 | Resin sealed type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04145645A (en) |
-
1990
- 1990-10-08 JP JP26985690A patent/JPH04145645A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4095827B2 (en) | Semiconductor device | |
US4994896A (en) | Semiconductor device | |
US20080258287A1 (en) | Semiconductor device and method of manufacturing the same | |
JP3893624B2 (en) | Semiconductor device substrate, lead frame, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
US20050056769A1 (en) | Chip scale package structure for an image | |
KR100548554B1 (en) | Test vehicle ball grid array package | |
JP2000040676A (en) | Manufacture of semiconductor device | |
JPH04145645A (en) | Resin sealed type semiconductor device | |
JPS63187657A (en) | Manufacture of semiconductor device | |
JPH09129796A (en) | Semiconductor device | |
JPH09129798A (en) | Electronic component and fabrication thereof | |
JP3179414B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH0547836A (en) | Mounting structure of semiconductor device | |
JPH07130937A (en) | Surface mounting type of semiconductor device, and lead frame used for its manufacture | |
KR100351926B1 (en) | Ball Grid Array package | |
JPH0730043A (en) | Semiconductor device and manufacture thereof | |
JPH0233961A (en) | Lead frame | |
JP2001223228A (en) | Semiconductor packaging board, manufacturing method and device thereof | |
JPH0582586A (en) | Semiconductor device and manufacture thereof | |
JPS5930535Y2 (en) | semiconductor equipment | |
JP3681856B2 (en) | Resin-sealed electronic components | |
JP2803260B2 (en) | Method for manufacturing semiconductor device | |
JP2507271Y2 (en) | Semiconductor device | |
KR100525091B1 (en) | semiconductor package | |
JPH04246852A (en) | Package for semiconductor device |