JPH04246852A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPH04246852A
JPH04246852A JP3011742A JP1174291A JPH04246852A JP H04246852 A JPH04246852 A JP H04246852A JP 3011742 A JP3011742 A JP 3011742A JP 1174291 A JP1174291 A JP 1174291A JP H04246852 A JPH04246852 A JP H04246852A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor device
lead
fixed
pattern recognition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3011742A
Other languages
Japanese (ja)
Inventor
Kenji Sugawara
健二 菅原
Yukio Kasuya
粕谷　行夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3011742A priority Critical patent/JPH04246852A/en
Publication of JPH04246852A publication Critical patent/JPH04246852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor device package where bonding inner leads are prevented from being wrongly recognized and lessened in trouble such as bonding deviation by a method wherein at least an inner lead provided with a pattern recognition recess is provided. CONSTITUTION:A lead frame 1 and a window frame 3 are fixed onto a ceramic board 7 through the intermediary of low melting point glass 2, a CCD long chip 4 is fixed on the ceramic board 7, electrodes 8 provided onto the CCD long chip 4 are electrically connected to the tips of inner leads 1b and an inner lead 1c provided with a bonding pattern recognition recess P with metal fine wires 5, and then a cap is fixed through the intermediary of thermosetting resin. In this semiconductor device package, the inner lead 1c provided with a bonding pattern recognition recess P is provided and discriminated from the other inner leads 1b, whereby inner leads are prevented from being wrongly recognized and lessened in defective bonding.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】この発明は、半導体装置用パッケ
ージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for a semiconductor device.

【０００２】0002

【従来の技術】従来のガラス封止型半導体装置は、図３
に示すように、セラミック基板７上に低融点ガラス２を
介し、内部リード１ｂが固着され、セラミック基板７上
にＩＣチップ５が固定さてた後に図４に示すようにＩＣ
チップ上の電極８と内部リード１ｂ先端部とを金属細線
６により電気的に接続し、低融点ガラス２もしくは熱硬
化型樹脂を介してキャップが固定され、半導体装置が形
成されていた。[Prior Art] A conventional glass-sealed semiconductor device is shown in FIG.
As shown in FIG. 4, the internal leads 1b are fixed on the ceramic substrate 7 through the low melting point glass 2, and after the IC chip 5 is fixed on the ceramic substrate 7, the IC is fixed as shown in FIG.
Electrodes 8 on the chip and the tips of internal leads 1b were electrically connected by thin metal wires 6, and a cap was fixed via low-melting glass 2 or thermosetting resin to form a semiconductor device.

【０００３】0003

【発明が解決しようとする課題】この従来の半導体装置
用パッケージでは、ＩＣチップ上の電極と、内部リード
を金属細線により導通させる場合、全ての内部リードに
おいて、先端の形状が単純であること、またリードフレ
ームを固定している低融点ガラスが光を反射することに
より、内部リードの位置を誤認識してしまいボンディン
グ不良となる場合が少なくなかった。[Problems to be Solved by the Invention] In this conventional semiconductor device package, when the electrodes on the IC chip and the internal leads are electrically connected by thin metal wires, the tips of all the internal leads must have a simple shape; Furthermore, when the low melting point glass that fixes the lead frame reflects light, the position of the internal lead is often misrecognized, resulting in defective bonding.

【０００４】特に、一次元固体撮像素子（ＣＣＤ）のよ
うなロングチップ用パッケージは、内部リード間隔が大
きいため誤認識となる場合が多く、ボンディング不良が
多発するといった問題点があった。In particular, packages for long chips such as one-dimensional solid-state imaging devices (CCDs) have problems in that erroneous recognition often occurs due to the large internal lead spacing, and bonding failures occur frequently.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体装置用パ
ッケージは、リードフレームがセラミック基板にガラス
を介して固着されてなるガラス封止型の半導体装置用パ
ッケージにおいて、内部リードの少なくとも１本の先端
に凹部を有して構成されている。[Means for Solving the Problems] A semiconductor device package of the present invention is a glass-sealed semiconductor device package in which a lead frame is fixed to a ceramic substrate through glass, in which at least one of the internal leads It is configured with a concave portion at the tip.

【０００６】[0006]

【実施例】次に本発明について図面を参照して説明する
。図１（ａ），（ｂ）はそれぞれ本発明の第１の実施例
の上面図およびＡ部拡大図である。セラミック基板７上
に低融点ガラス２を介し、リードフレーム１及びウイン
ドフレーム３が固着され、セラミック基板上にＣＣＤロ
ングチップ４が固定された後にＣＣＤロングチップ上の
電極８と内部リード１ｂ，凹部Ｐ付の内部リード１ｃ先
端部とを金属細線６による電気的に接続し、熱硬化型樹
脂を介してキャップが固定される半導体装置用パッケー
ジである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIGS. 1A and 1B are a top view and an enlarged view of part A of a first embodiment of the present invention, respectively. The lead frame 1 and the wind frame 3 are fixed on the ceramic substrate 7 via the low melting point glass 2, and after the CCD long chip 4 is fixed on the ceramic substrate, the electrode 8, internal lead 1b, and recess P on the CCD long chip are fixed. This is a package for a semiconductor device in which the tip of an internal lead 1c attached thereto is electrically connected by a thin metal wire 6, and a cap is fixed via a thermosetting resin.

【０００７】本実施例の半導体装置用のパッケージでは
、ボンディングパターン認識用の凹部Ｐ付き内部リード
１ｃを設け、他の内部リード１ｂと区別することにより
リード誤認識を防止してボンディング不良を低減する。 特に、一次元ＣＣＤのようなロングチップ用パッケージ
は、内部リード認識範囲が縦長である為、寸法誤差が大
きく、凹部付き内部リード１ｃのパターン認識により誤
認識を防止することが出来る。In the package for a semiconductor device of this embodiment, an internal lead 1c with a recess P for bonding pattern recognition is provided, and by distinguishing it from other internal leads 1b, erroneous recognition of the lead is prevented and bonding defects are reduced. . In particular, in a long chip package such as a one-dimensional CCD, the internal lead recognition range is vertically long, so dimensional errors are large, and erroneous recognition can be prevented by pattern recognition of the internal leads 1c with recesses.

【０００８】図２は本発明の第２の実施例の一部拡大斜
視図で、Ｖ字型の凹部Ｑを内部リードに有している。FIG. 2 is a partially enlarged perspective view of a second embodiment of the present invention, which has a V-shaped recess Q in the inner lead.

【０００９】これらの形状のリードフレームは、従来の
エッチングプレス技術を用いて容易に形成が可能である
。本発明型の内部リード形状によるボンディング不良率
は０．０４％であり、従来型の内部リードの場合の不良
率３．９８％の１００分の１に改善された。Lead frames having these shapes can be easily formed using conventional etching press technology. The bonding failure rate due to the internal lead shape of the present invention type was 0.04%, which was improved to 1/100 of the failure rate of 3.98% in the case of the conventional internal lead.

【００１０】0010

【発明の効果】以上説明したように本発明は、パターン
認識用の凹部付き内部リードを少なくとも１本設けるこ
とにより、ボンディング内部リード誤認識を防止し、ボ
ンディングずれなどの不良を１００分の１に低減するこ
とが出来るという効果を有する。As explained above, the present invention prevents erroneous recognition of bonding internal leads by providing at least one internal lead with a recess for pattern recognition, and reduces defects such as bonding misalignment to 1/100. It has the effect of being able to reduce

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】（ａ），（ｂ）はそれぞれ本発明の第１の実施
例の平面図およびＡ部拡大図である。FIGS. 1A and 1B are a plan view and an enlarged view of part A of a first embodiment of the present invention, respectively.

【図２】本発明の第２の実施例の一部拡大斜視図である
。FIG. 2 is a partially enlarged perspective view of a second embodiment of the invention.

【図３】従来の半導体装置の一例の斜視図である。FIG. 3 is a perspective view of an example of a conventional semiconductor device.

【図４】図３のＢ部拡大図である。FIG. 4 is an enlarged view of part B in FIG. 3;

【符号の説明】[Explanation of symbols]

１　　　　リードフレーム １ａ　　　　外部リード １ｂ　　　　内部リード １ｃ　　　　凹部付き内部リード ２　　　　低融点ガラス ３　　　　ウインドフレーム ４　　　　ＣＣＤロングチップ ５　　　　半導体素子 ６　　　　金属細線 ７　　　　セラミック基板 Ｐ，Ｑ　　　　凹部 1 Lead frame 1a External lead 1b Internal lead 1c Internal lead with recess 2 Low melting point glass 3 Wind frame 4 CCD long chip 5 Semiconductor device 6 Thin metal wire 7 Ceramic substrate P, Q　　　Concavity

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　リードフレームがセラミック基板にガ
ラスを介して固着されてなるガラス封止型の半導体装置
用パッケージにおいて、内部リードの少なくとも１本の
先端に凹部を有していることを特徴とする半導体装置用
パッケージ。1. A glass-sealed semiconductor device package in which a lead frame is fixed to a ceramic substrate via glass, characterized in that at least one of the internal leads has a recess at the tip. Packages for semiconductor devices.
JP3011742A 1991-02-01 1991-02-01 Package for semiconductor device Pending JPH04246852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3011742A JPH04246852A (en) 1991-02-01 1991-02-01 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3011742A JPH04246852A (en) 1991-02-01 1991-02-01 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPH04246852A true JPH04246852A (en) 1992-09-02

Family

ID=11786479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3011742A Pending JPH04246852A (en) 1991-02-01 1991-02-01 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPH04246852A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888209B2 (en) 2002-09-20 2005-05-03 Casio Computer Co., Ltd. Semiconductor package and method of fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242254B2 (en) * 1976-09-20 1987-09-07 Intaanashonaru Bijinesu Mashiinzu Corp
JPH02246256A (en) * 1989-03-20 1990-10-02 Hitachi Ltd Semiconductor element package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242254B2 (en) * 1976-09-20 1987-09-07 Intaanashonaru Bijinesu Mashiinzu Corp
JPH02246256A (en) * 1989-03-20 1990-10-02 Hitachi Ltd Semiconductor element package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888209B2 (en) 2002-09-20 2005-05-03 Casio Computer Co., Ltd. Semiconductor package and method of fabricating the same

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Effective date: 19970506