JPH02246256A - Semiconductor element package - Google Patents

Abstract

PURPOSE:To mount a package readily and automatically by making facing leads parallel, and lowering the package into the pin-inserting holes of a board vertically. CONSTITUTION:Leads are held between a lower ceramic substrate LOW and an upper ceramic frame UPP and fixed with frit glass FLT. The outer leads OL are made to protrude horizontally from the parts between the lower and upper ceramic bodies LOW and UPP and bent downward. The facing outer leads OL are in parallel. An angle theta1 formed with the outer lead OL and the upper ceramic frame UPP is made to be 90-93 deg.. Therefore, a semiconductor package can be readily inserted into the pin inserting holes of a printed wiring board readily by only lowering the package vertically. Thus, the package can be mounted automatically without deforming the outer leads.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor element package mounting a semiconductor element, and particularly relates to a semiconductor element package suitable for automatic mounting on an external application circuit such as a printed wiring board. .

[Conventional technology]

Semiconductor integrated circuit packages can be categorized by material: plastic packages using resin molding technology, ceramic packages using ceramic wiring boards,
There are three types of glass-sealed packages in which leads are sandwiched between two ceramic plates and sealed with low-melting glass. If the leads are arranged parallel on two sides, it is DIL.
(Dual-In-Line)
), and is the most popular type, and the three types of packages mentioned above are DILP, ILC, and DI, respectively.
Also called LG. DILG is also called ``Sardip''. From a cost perspective, DILP, DILG
, DILC, and in terms of reliability such as moisture resistance, DI
The highest order is LC, DILG, and DILP.

DILG and DILP leads involve an assembly process such as cutting and bending the lead frame, and the shape of the normal lead (leg) is mainly one that opens diagonally, as shown in Figure 4. .

For solid-state imaging devices, see 1, for example, Video Information 25-3 published by Japan Industrial Development Corporation, May 1, 1986.
It is written on page 1.

[Problem to be solved by the invention]

In a conventional semiconductor device package, the outer leads that protrude horizontally from the two sides of the package body are bent downward a little beyond the outer leads, but the opposing outer leads are In Figure 9, which is open in a "V" shape as shown in Figure 9, LOW is the lower ceramic substrate, UPP is the upper ceramic frame, FIT is the frit glass, and OL is the outer lead. Outer lead OL and upper ceramic frame UP
The angle θ1 between P and the upper surface is 96 to 1006.

For example, when mounting a semiconductor element package for semiconductor memory such as D-RAM (dynamic RAM) on an external application circuit such as a printed wiring board using an automatic inserter, both expanding outer leads are placed on the top surface of the package body. The package is mounted by inserting it with an automatic inserter from the outside of the surface of the outer lead so as to be perpendicular to the outer lead, inserting it into the pin insertion hole of the printed wiring board, and pushing the top surface of the package body. After inserting the semiconductor element package into the printed wiring board, the elastic outer leads return to the original open state, making it difficult for the semiconductor element package to come off the printed wiring board, and soldering etc. can be done easily and automatically. can.

However, in the case of a solid-state imaging device, the solid-state imaging device (semiconductor element package) is first assembled into a sensor holder (also called a lens unit) before being mounted on a printed wiring board. Align the center of the array with the center of the optical axis of the lens,
This is to prevent ``field vignetting, image distortion, and image blur,'' and to mount a crystal plate and infrared cut filter together. Therefore, it is difficult to insert the outer lead with an automatic inserter because the holder gets in the way. Further, as described above, in the solid-state imaging device, most of the center of the upper surface of the package body is occupied by the window glass. As mentioned above, the automatic inserter is installed by pushing the top of the package. Therefore, even when inserting a solid-state imaging device directly into a printed circuit board, pushing the top surface of the device can easily damage the window glass or attract foreign matter. It appears as a black mark on the screen. As described above, it is difficult to automatically insert a solid-state imaging device into a printed wiring board.

An object of the present invention is to provide a semiconductor element package that is easy to mount on an external application circuit such as a printed wiring board.

Another object of the present invention is to provide a solid-state imaging device that is easy to automatically mount.

[Means to solve the problem]

In order to achieve the above object, a semiconductor element package of the present invention includes a lead having an inner lead and an outer lead electrically connected to electrodes of the semiconductor element, and a package body holding the semiconductor element and the lead. , the outer leads protrude horizontally from at least two side surfaces of the package body, are bent downward, and at least the tips of the opposing outer leads are parallel.

It is desirable that the angle formed between at least the tip of the outer lead and the upper surface of the package body is 90 to 936 degrees.

Further, the outer lead is bent in the downward direction in the vicinity of the portion protruding from the package body, and
The outer leads may be bent again toward the opposing outer leads at a portion slightly beyond that point, and the remaining opposing outer leads may be made parallel.

Furthermore, the package body is configured with two package bodies, an upper and a lower package body, and the outer leads are made to protrude from between the two package bodies, and the width of the lower package body between the opposing outer leads is equal to the width of the upper package body. It may be configured to be smaller than the width of the body.

[Effect]

In the semiconductor device package of the present invention, the outer leads are bent at right angles to the top surface of the package body, and at least the tips of the opposing outer leads (hereinafter referred to as opposing leads) are parallel, so that the semiconductor device package can be connected to a printed wiring board. It can be easily inserted by simply lowering it vertically into the pin insertion hole. In other words, it is no longer necessary to insert the opposing leads, which have been spread out by an automatic inserter, so that they are at right angles, and the outer leads are deformed. Furthermore, since the opposing leads of the solid-state imaging device incorporated in the sensor holder are parallel, automatic mounting can be easily performed by holding the holder with an automatic inserter. Therefore, solid-state imaging devices can be made into solid-state imaging devices and made into plastic packages, and product costs can be significantly reduced compared to the expensive laminated type ceramic packages that have been common in the past.

Further, the outer lead is bent in the direction of opening downward from the package body near the point where it protrudes from the package body,
Of course, a similar effect can be obtained even if the outer lead is bent again at the tip thereof and the opposing leads are parallel to each other. With such a configuration, the strength of the bent portion of the outer lead can be increased.

Furthermore, by configuring the package body with two package bodies, upper and lower, with the outer lead protruding from between the two package bodies, and by configuring the width of the lower package body between the opposing leads to be smaller than the width of the upper package body. When using a conventional lead frame in which the outer leads are opened in a "V" shape and bending the outer leads at a right angle after fixing the lead frame between the upper and lower package bodies, there is a margin to hold the bent shoulders of the outer leads. The degree of accuracy can be increased, and the tolerance of external dimensions can be reduced.

〔Example〕

FIGS. 5(a) to 5(d) are diagrams showing the structure of a solid-state imaging device to which the semiconductor element package of the present invention is applied, and the overall structure will be described below. DVC1 solid-state imaging chip C
The portion (container) of the solid-state imaging device DVC excluding the HI is referred to as a package PKG.

In the same figure, (a) shows the solid-state imaging device DVC connected to the chip C.
FIG. 3 is a top view when viewed from the light-receiving surface side of the HI. Top view (
Based on a), (b) is a side view when viewed from above, (c) is a sectional view taken along the c-c cutting line, (d) is a side view when viewed from the right side, and (e) is a side view when viewed from the right side. FIG. 3 is a cross-sectional view taken along the line e-a.

The window glass GLS is a translucent sealing plate and is made of a glass material such as borosilicate glass (BsOs.Sin).

The solid-state imaging chip CHI is made using monolithic semiconductor integrated circuit technology, and has multiple photoelectric conversion elements such as photodiodes arranged on the surface (light receiving surface) on the window glass GLS side, and an adhesive such as silver paste material on the back surface. It is bonded to the lower ceramic substrate LOW using an adhesive.

The lower ceramic substrate LOW has a mount part MN, which is a recessed part for mounting the solid-state imaging chip CHI, in the center thereof.
This concave portion adjusts the height relationship between the solid-state imaging chip CHI and the inner lead IL.

The upper ceramic frame UPP has a light-receiving window WDW cut out in the center so that external light hits the solid-state imaging chip CHI.

The lead LD is a lead for electrically connecting between the solid-state imaging chip CHI and an external application circuit such as a printed wiring board, and is connected to the CHI using a frit glass FLT between the upper and lower ceramic bodies UPP and LOW. Inner lead part IL for connection and outer lead part OL for connection with external circuit
Both lead portions are formed continuously (integrally) with the lead frame REF. The inner lead IL has the same tip shape as the 16 inner leads ILI located in the middle and a round hole in the center.

There are a total of 20 inner leads IL2, each with a thick tip shape and four inner leads located at the four corners. This inner lead IL
The special shape of No. 2 is useful for lead position pattern recognition during automatic wire bonding.

The bonding wire WIR is a metal wire made of AI, Au, etc., for electrically connecting the inner lead L and the bonding pad of the solid-state imaging chip CHI. Because of the recess of the mount MNT, the solid-state imaging chip C
Since the upper surface of HI is lower than the upper surface of inner lead IL, it is possible to prevent the bonding wire WIR from hanging down and coming into contact with the edge of solid-state imaging chip CHI, thereby causing a short circuit.

Reference holes HL1 and HL2 are formed in the metal plates REFI and REF2. When the solid-state imaging chip CHI is automatically die-bonded to the mount part MNT, its positioning is performed based on the reference holes HLI, HL2 and/or the inner lead IL2.
The relative positions of LI, HL2 and solid-state imaging chip CHI are set with high precision. Therefore, the solid-state imaging device DVSttV
When mounting on applied products such as TR cameras, use the reference hole HL1.
, HL2 as a positioning reference, it is possible to align the center of the lens of the applied product with the center of the photodiode array of the solid-state imaging chip CHI with high precision.

The recess IDX is a recess provided in the upper and lower ceramic bodies UPP and LOW, and is an index indicating the circuit arrangement reference position of the 20 outer leads ILL.

Next, a method for assembling the solid-state imaging device DVS will be briefly described.

First, the lead LD and the reference edible metal plate REFI.

A lead frame in which REF2 etc. are connected is formed from a single metal plate by press molding or etching. As a metal material, for example, 42 is compatible with ceramics.
70i is selected.

Next, a lead frame with the outer lead OL bent almost vertically is placed on the lower ceramic substrate LOW, which has frit glass FLT coated in a frame shape on the high part around the mount part MNT, and is sandwiched between the upper ceramic frame UPP. They are fused together using frit glass FLT.

Next, the solid-state imaging chip CHI is automatically die-bonded to the mount portion MNT, and automatic wire bonding is performed between the inner lead IL and the solid-state imaging chip CHI using a bonding wire WIR.

Next, the window glass GLS is attached to the upper ceramic frame Upp using an organic adhesive or the like.

Finally, cut off the unnecessary parts of the lead frame.

20 7 Uta lead OLs and reference edible metal plate REF1.
Separate each of REF2. Reference hole metal plate REF1 shown in the top view of (a). The convex portion BRD of REF2 is the remains after removing an unnecessary bridge portion.

FIG. 1 is a cross-sectional view showing the main parts of such a solid-state imaging device DVC when the present invention is applied thereto. (The same is true for FIGS. 2 and 3, which mainly shows the upper and lower ceramic plates UPP, LOW, outer lead OL, and frit glass FLT, and the detailed parts are the same as in FIG. 5.) The solid-state imaging device of this embodiment In DVC, solid-state imaging chips (
Inner lead I electrically connected to the electrode (not shown)
L and a lead having an outer lead OL continuous thereto,
Upper and lower ceramic bodies that hold the solid-state imaging chip and leads;
That is, it has a lower ceramic substrate LOW and an upper ceramic frame UPP. The lead is on the lower ceramic board LO
It is sandwiched between W and the upper ceramic frame UPP and fixed with frit glass FLT. The outer lead OL protrudes horizontally from between the upper and lower ceramic bodies LOW and UPP (that is, from the two side surfaces of the upper and lower ceramic bodies) and is bent downward, so that the opposing outer leads OL are parallel to each other. An angle 01 between the outer lead OL and the upper surface of the upper ceramic frame UPP is 90 to 93@.

The leads are formed by etching, for example, a 4270 material with a wall thickness of 0.25 mm, and the inner lead IL is coated with AJ by vapor deposition. A flat lead frame may be sandwiched and fixed between the upper and lower ceramic bodies LOW and UPP, and then the outer leads OL may be bent. You can also fix it with a sandwich.

Here, the latter method was used, and the radius of curvature R of the bent shoulder S was about 0.2 m, and the wall thickness of the shoulder S was about 0°22㎜. The distance between the opposing outer leads OL (hereinafter referred to as the opposing lead distance) is the target value of 20.
Actual value is 20.38 for 32, 0.3 from shoulder S
The distance between the opposing leads at the 8th position was 20.27m against the same target value. Further, the total length of the outer lead OL was 6.2 m, and the opposing lead was slightly open in a "V" shape, but the angle θ1 formed with the upper surface of the upper ceramic frame UPP was 90.51. Since the shoulder S of the outer lead OL was bent at a right angle, there was concern about the bending fatigue strength of the lead, but when we conducted the test, the number of bends was 14, which was much higher than the standard of 3 or more specified by JIS ( JIS C-5035 test of JIS C-7022A-11 method test).

A color solid-state imaging chip was mounted on this package PKG, sealed with window glass, incorporated into a sensor holder, and mounted on a printed wiring board. As a result, outer lead O
L smoothly entered the bottle insertion hole of the printed wiring board. In this case, the automatic inserter was inserted with the sensor holder in between.

In the above embodiment, a lead frame (etched lead) formed by etching was used.

Lead frame (breath lead) formed by press molding with low unit cost to reduce package cost.
We will explain the case using . The shape of the lead frame is similar to that of an etched lead. The angle θ□ between the outer lead and the top surface of the upper ceramic frame is 90.4@
Met. As a result of measuring lead bending fatigue strength, the number of bending times was 3, which was just below the standard value. Therefore, in order to further improve the strength, we attempted to change the lead bending part.

In order to improve the strength, it is effective to alleviate the stress on the shoulder by increasing the radius of curvature of the bending shoulder S of the outer lead and increasing the wall thickness of the shoulder. In the case of the etching lead, the radius of curvature R of the shoulder was 0.2 degrees, so this time R=0.
3), the angle θ1 between the outer lead and the upper surface of the upper ceramic frame was 96°, which did not satisfy the target angle of 90 to 931. As shown in the schematic cross-sectional view of the imaging device (half omitted), approximately 111 points below the shoulder S of the outer lead.
At the standoff part SO of I, the lead extending from the shoulder part S was bent again by 6 to 15 degrees. At this time,
The remaining θ, including the tip of the outer lead OL, is 90.
．． It was 7°. When the bending fatigue strength of the shoulder S was measured, it was found that the strength was improved by about 6 times, and the JIS
The above standard values were well exceeded. After mounting a solid-state imaging chip in a package with this outer lead shape and sealing it with window glass, it was assembled into a sensor holder and mounted on a printed wiring board, and it could be inserted smoothly using an automatic inserter.

As a method for bending the outer leads at right angles to the upper surface of the upper ceramic frame, there are two methods, as described above, in which a lead frame with the outer leads bent at right angles is sandwiched and fixed between the upper and lower ceramic bodies. After fixing it between the upper and lower ceramic bodies,
Another method is to bend the outer lead at a right angle.

In the conventional lead frame, the angle θ3 of the outer lead with respect to the upper surface of the upper ceramic frame body is 96 to 100' and opens in a "V" shape, but after using this as it is and fixing it by sandwiching it between the upper and lower ceramic bodies.

A method of bending the outer lead at right angles by applying force from outside the surface of the outer lead will be explained. In this case, external force is applied to the frit glass to which the outer lead is fused, and cracks may occur. In order to minimize this crack, the bending shoulder S of the outer lead
It is sufficient to hold the part and apply force, but it is necessary to have some tolerance in the part to be held.

Generally, the spacing between opposing leads is 2.54a (100 sets i1)
is an integer multiple of In order to maintain this spacing and accommodate the above method, the width of the lower ceramic substrate between opposing leads was reduced. The width of the upper ceramic frame may also be made smaller to match the lower ceramic substrate, but the sealing width and sealing margin with the window glass will become smaller.

Since the reliability decreases, it is better to reduce the width of only the lower ceramic substrate, and if only the width of the upper ceramic frame is increased, there are advantages as described below. That is, the external dimensions of the upper and lower ceramic bodies also include the alignment tolerance between the upper ceramic frame and the lower ceramic substrate.

Generally, the machining accuracy for a single ceramic is at most 0.2 m for about 20 m, but the assembly accuracy for the upper ceramic frame and the lower ceramic substrate is at most 0.3 m. Therefore, the outer dimension tolerance of the upper and lower ceramic bodies is required to be approximately 0.45 mm. By making the lower ceramic substrate smaller (for example, by 0.3 mm), the assembly precision is absorbed, so the tolerance of the external dimensions can be reduced, and the tolerance of the upper ceramic frame is 0.2 mm. You can hold up to. Further, in this case, the position of the semiconductor chip can be set with high precision with reference to the end face of the upper ceramic frame, which is also advantageous for pellet attachment of the solid-state imaging chip.

Note that the present invention is not limited to the above-mentioned embodiments, and of course can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, a solid-state imaging device mounted with a solid-state imaging chip and having an optical window was described as an example, but it is of course applicable to a semiconductor element package in which other semiconductor elements are mounted. In addition, in the above embodiment, the upper and lower 2
Although the package is made up of a single package body, it may be made up of a single package body, and the material of the package is not limited to ceramic.

〔Effect of the invention〕

As explained above, in the semiconductor element package of the present invention, the opposing leads are parallel, so when mounting the package on an external application circuit, it can be easily and automatically mounted by simply lowering the package vertically into the pin insertion hole of the board. I can do it. Furthermore, when the package of the present invention is applied to a solid-state imaging device, it can be easily and automatically mounted using an automatic inserter, and the solid-state imaging device can be made into a solid-state imaging device or a plastic package, making it possible to significantly reduce product costs. .

[Brief explanation of drawings]

1 is a schematic cross-sectional view of a solid-state imaging device according to a first embodiment of a semiconductor element package of the present invention, FIG. 2 is a schematic cross-sectional view of a solid-state imaging device according to a second embodiment of the present invention, and FIG. The figures are a schematic sectional view of a solid-state imaging device according to a third embodiment of the present invention;
The figure is a schematic side view of a conventional semiconductor element package.
Figures (a) to (d) are diagrams showing solid-state imaging devices to which the semiconductor element package of the present invention is applied, in which (a) is a top view of the solid-state imaging device, and (b) is a view from above of (a). (c) is a cross-sectional view taken along the a-c cutting line in (a),
(d) is a side view when seen from the right side of (a), and (e) is a sectional view taken along the line ee in (a). LOW...Lower ceramic substrate UPP...Upper ceramic frame CHI...Solid-state imaging chip FLT...Flit glass REFI, REF2...Reference edible metal plate OL...Outer lead IL...Inner lead S ...Bending shoulder part So...Standoff part θ θ2, θ, ...Angle between the outer lead and the top surface of the package body Fig. 1 Fig. 2

Claims (3)

[Claims] 1. A lead having an inner lead and an outer lead electrically connected to an electrode of a semiconductor element, a package body holding the semiconductor element and the lead, the outer lead protruding horizontally from at least two side surfaces of the package body, A semiconductor device package characterized in that at least the tips of the opposing outer leads are parallel to each other and are bent downward. 2. The outer leads are bent in the downward opening direction near the point protruding from the package body, and a little beyond that, the outer leads are bent again toward the opposing outer leads, and the remaining opposing leads are bent again toward the opposing outer leads. 2. The semiconductor device package according to claim 1, wherein said outerries are parallel. 3. The package body consists of two package bodies, an upper and a lower package body, and the outer lead protrudes from between the two package bodies, and the width of the lower package body between the opposing outer leads is greater than the width of the upper package body. 3. The semiconductor device package according to claim 1, wherein the semiconductor device package is small.