JPH0414501B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for forming fine patterns with high pattern accuracy.

(b) Background of the technology The degree of integration of semiconductor devices such as ICs and LSIs is becoming larger and larger, and at the same time, the unit elements are becoming smaller.As a result, electrode pattern widths and conductor pattern widths also become minute, and those on the [μm] scale are now used. ing. Therefore, in order to increase the degree of integration, it is necessary not only to improve the positional accuracy of the pattern, but also to improve the etching accuracy and to minimize the difference (clearance) between the resist dimension and the design dimension of the pattern.

(c) Prior art and problems Thin film formation technology and photolithography are used to form patterns for semiconductor devices, and fine patterns with widths on the order of micrometers are formed. Patterns are designed with considerable clearance in mind, and the cause of this is the side etching phenomenon that occurs during plasma etching.

The problems will be explained below using the case of forming the gate of a MOS transistor as an example.

FIG. 1 is a cross-sectional view of a MOS transistor. On a silicon (Si) substrate 1, there is a thick oxide film 2 for isolation between elements, surrounded by a thin oxide film 3.
A gate 4 is provided on this, and an insulating layer 5 made of phosphosilicate glass (PSG for short) is provided on both sides of the gate 4.
Source 6 and drain 7 electrodes made of an aluminum vapor-deposited film and connected to the ion-implanted region of the Si substrate 1 through windows are formed at the same time as the wiring pattern. Here, photo-etching technology is used to form fine patterns such as patterning the gate 4 and opening windows in the PSG insulating layer 5, but the higher the degree of integration of the device, the closer these patterns can be formed to the designed values. It is necessary to. Photo-etching involves leaving a fine pattern coated with photoresist and etching the substrate using chemical etching or dry etching to form a fine pattern.
Currently, a dry etching method is often used from the viewpoint of etching accuracy.

Here, the dry etching method performs etching using gas ions generated by causing discharge in a reduced pressure gas atmosphere, but the degree of vacuum used,
Etching forms differ depending on the type of gas, voltage application method, discharge frequency, etc., and include plasma etching, reactive ion etching, chemical etching, etc.
It is distinguished from dry etching, ion milling, etc.

The dry etching methods used to form fine patterns in connection with the present invention are plasma etching and reactive ion etching.

In other words, plasma etching involves introducing a gas such as _CF4 into a reduced pressure reaction chamber, and then using high-frequency discharge to
Active species such as radicals are generated and etched by a chemical reaction with the object to be etched in the reaction chamber.

On the other hand, in reactive ion etching, the object to be etched is placed on the cathode, which is connected to a high frequency power source of 13.56 [MHz] on one side of parallel plate electrodes.
Etching is performed by promoting a chemical reaction using the energy of positive ions in the gas plasma bombarding the object to be etched on the cathode due to the cathode drop voltage. Anisotropic etching is performed, and etching is performed in a direction perpendicular to the electrode. be done.

Comparing these two etching methods, reactive ion etching is superior in terms of accuracy, but when etching pattern areas with steps, etching residues are produced at the steps due to uneven resist film thickness. Currently, a plasma etching method is used.

However, since this method is isotropic etching, the phenomenon of side etching is unavoidable.

FIG. 2 shows an enlarged view of the state in which the gate 4 in FIG.
A photoresist layer 9 is formed on the poly-Si layer 9 by spin coating, and exposed and developed to remove the photoresist layer 9 except for the gate 4, and the excess poly-Si layer 8 is removed by plasma etching.
The state in which the gate 4 is formed by removing the gate 4 is shown. However, since this etching method is isotropic etching, the etching process is twice as thick as the poly-Si layer 8.
A side etch 10 of three times the size is formed, so that the width of the gate 4 made of the poly-Si layer 8 is much smaller than the width of the mask made of the photoresist layer 9.

Conventionally, masks were formed taking into account the reduction in the side etching portion 10, but it was difficult to match the expected width of the side etching with the actual width, and the degree of integration increased because the pattern was designed to be that large. There was a problem that it wasn't.

Furthermore, when forming semiconductor devices, a large number of devices are fabricated simultaneously on the same wafer, but in this case, the etching speed is not uniform over the entire surface of the wafer, and the etching speed is higher on the outer periphery than on the center, so it is difficult to form a pattern. It was inevitable that variations in etching would occur.

(d) Object of the invention The object of the invention is to provide a method that can form fine patterns with high pattern accuracy.

(e) Structure of the Invention The purpose of the present invention is to form a thin film pattern of the conductor on the substrate when forming a conductor pattern on a semiconductor substrate, and then epitaxially grow the same material on the pattern to a predetermined thickness. This can be achieved by a method for forming a fine pattern, which is characterized in that at least pattern formation is performed.

(f) Embodiments of the Invention The present invention improves the selective epitaxial growth technique performed using the chemical vapor deposition method (CVD method), and enables crystal growth with good dimensional accuracy or heterocrystalline growth to be performed on single crystals and polycrystals. This was done because it has come to be used for all types of cases.

An embodiment in which the gate of a MOS transistor is formed in the same manner as shown in FIG. 2 will be described below.

3A to 3C show the process according to the present invention. First, a thin oxide film 3 with a thickness of about 5000 [Å] is coated.
Thin (e.g. 400 Å) poly-Si layer 1 by CVT method
A mask 12 made of a photoresist layer is formed on the mask 12 with dimensions according to the designed values, and a gate pattern is formed by etching using a plasma etching method. Here, since the poly-Si layer 11 is thin, the side etching phenomenon does not appear as shown in FIG.

Next, the mask 12 made of a photoresist layer is removed, as shown in FIG.

Next, by performing selective crystal growth using the CVD method, a poly-Si layer 13 is selectively grown on the poly-Si layer 11 to form a gate 4 with a thickness of about 4000 [Å]. C.

Recently, patterns have been formed by coating conductor patterns with tungsten (W), molybdenum (Mo), etc. in order to lower the resistance of the conductor patterns, but in this case, as shown in Figure 4, poly-Si
A poly-Si layer 14 is selectively grown on the layer ₁₁ to _be thinner than that shown in FIG. The gate 4 with a thickness of about 4000 Å can be made by selectively growing metals such as W and Mo by CVD as a medium.

By selectively growing a poly-Si layer or a metal layer in this way, minute patterns can be accurately formed and the degree of integration of semiconductor devices can be increased.

(g) Effects of the Invention In the present invention, when forming a pattern by plasma etching, side etching is unavoidable, and the pattern is formed by anticipating this reduction in area in advance, which leads to a decrease in accuracy and a decrease in the degree of integration in fine pattern formation. This was done to improve the disadvantages, and by implementing the present invention, it has become possible to form fine patterns with high pattern accuracy.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional structural diagram of a MOS transistor, Fig. 2 is a cross-sectional view illustrating side etching during gate formation, Fig. 3 A to C are process diagrams for implementing the present invention, and Fig. 4 is another implementation. FIG. 3 is an example cross-sectional view. In the figure, 1 is a silicon substrate, 3 is a thin oxide film, 4 is a gate, 8 is a polysilicon layer, 9 is a photoresist layer, 10 is a side etching part, 11,
13 and 14 are polysilicon layers, and 15 is a tungsten layer.

Claims (1)

[Claims] 1. When forming a conductor pattern on a semiconductor substrate, a thin film pattern made of the conductor is formed on the substrate, and then the same material is epitaxially grown on the pattern to a predetermined thickness to form the pattern. A method for forming fine patterns.