JPH04142624A - Interruptive circuit of processor - Google Patents

Abstract

PURPOSE:To make a processor possible to effectively evaluate a microprogram by providing the processor with an interruptive control circuit for generating an interrupt at an interrupt level indicated by an interrupt level register when outputting a count zero signal from the counter section of the processor. CONSTITUTION:The processor consists of a counter section 4 for outputting a count zero signal when a counting result counted every time a microprogram instruction is executed becomes zero, an interrupt level register 5 for specifying an interrupt level, and an interrupt control section 3 for generating an interrupt at the interrupt level specified by the interrupt level register 5 when the counter section 4 outputs the count zero signal. Accordingly, when a result of the execution of a microinstruction becomes zero, an interrupt can be executed at an arbitrary point of time when an interrupt level is specified. With this, a microprogram can be effectively evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processor interrupt circuit, and more particularly to a microprocessor interrupt circuit that generates an interrupt to a processor executing microinstructions.

[Conventional technology]

Conventional processor interrupt circuits are not provided with means for generating an interrupt at any location in a microprogram while the processor is executing the microprogram.

[Problem to be solved by the invention]

The conventional processor interrupt circuit described above does not have a means to generate an interrupt at any point in the microprogram during the execution of the microprogram, so it is not possible to generate an interrupt in a timely manner and the microprogram is interrupted. The evaluation could not be carried out sufficiently.

[Means to solve the problem]

The interrupt circuit of the processor of the present invention includes, in a processor that executes a microinstruction, a counter section that outputs a count zero signal when the count result counted every time the microinstruction is executed becomes zero, and an interrupt level that outputs a count zero signal. and an interrupt control unit that generates an interrupt at the interrupt level indicated in the interrupt level register when the counter unit outputs a count zero signal.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The microprogram is stored in the microinstruction storage section 1, and the microinstruction execution section 2 reads and executes the microprogram stored in the microinstruction storage section 1 in response to the address control signal 6. Further, the microinstruction execution unit 2 notifies the counter unit 4 that the microinstruction has been executed by activating the count signal 7. The counter unit 4 recognizes the execution of the microinstruction when the count signal 7 becomes active, and sets the counter to 1. Further, the counter section 4 increments the counter by -1 so that the count value becomes 0, and when the count is exhausted, the counter section 4 activates the count zero signal 8 and notifies the interrupt control section 3. Interrupts by interrupt signal 9 are controlled, and when count zero signal 8 becomes active, an interrupt is generated according to the interrupt level indicated in interrupt level register 5, and the interrupt is sent to microinstruction execution unit 2. Notify of occurrence.

In this way, the interrupt level value to be generated, for example, 7A, is set in the interrupt level register section 5, and the number of microinstruction steps up to the address at which the interrupt is to be generated during the microprogram, for example, 10, is set in the counter section 4. , execute the microprogram. The microinstruction execution unit 2 reads out and executes microinstructions from the microinstruction storage unit 1, and outputs a count signal 7 to the counter unit 4. The counter section 4 subtracts -1 from the count value 10 initially set by the count signal 7. When the counter unit 4 becomes 0 as a result of subtraction,
That is, when the microinstruction execution unit 2 executes a 10-step microinstruction, it requests the interrupt control unit 3 to generate an interrupt using the count zero signal 8. The interrupt control unit 3 is
The count 0 signal causes an interrupt of level 7A set in the interrupt level register 5 to be generated.

〔Effect of the invention〕

As explained above, the present invention generates an interrupt when the execution result of a microinstruction becomes 0 and an interrupt level is specified, so that an interrupt can be generated at any point in a microprogram, and the microprogram can be effectively evaluated. It can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

Claims (1)

[Claims] In a processor that executes a microinstruction, a counter section that outputs a count zero signal when a count result counted every time the microinstruction is executed becomes 0;
The present invention is characterized by comprising an interrupt level register that indicates an interrupt level, and an interrupt control unit that generates an interrupt at the interrupt level indicated in the interrupt level register when the counter unit outputs a count zero signal. Processor interrupt circuit.