JPS57153342A - Pipeline computer - Google Patents

Pipeline computer

Info

Publication number
JPS57153342A
JPS57153342A JP4016181A JP4016181A JPS57153342A JP S57153342 A JPS57153342 A JP S57153342A JP 4016181 A JP4016181 A JP 4016181A JP 4016181 A JP4016181 A JP 4016181A JP S57153342 A JPS57153342 A JP S57153342A
Authority
JP
Japan
Prior art keywords
instruction
signal
branch
pushup storage
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4016181A
Other languages
Japanese (ja)
Inventor
Jiro Suzaku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4016181A priority Critical patent/JPS57153342A/en
Publication of JPS57153342A publication Critical patent/JPS57153342A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Abstract

PURPOSE:To remarkably improve an instruction stream through a branch instruction, by commonly using the hardware for address computation and using a requesting function from an essential execution processor to a pushup storage processor at the start of instruction. CONSTITUTION:A pipeline computer consists of 1-set buffers 5-8, an instruction register 9, an instruction CUEs 10a-10d, an operand address computing adder 11, a register 12, a control block 14, and a control circuit 16. The register 12 stores a branched address with the instruction of a signal 13, when a condition branch instruction with higher probaility for branch success is interpreted at the instruction interpretation of a pushup storage processor. The control block 14 changes an instruction stream and generates a signal requesting a new instruction stream to the branch buffers 5-8. On the other hand, the control circuit 16 is reset with a signal 17, when it is different from the estimated operation of the pushup storage operation at the execution time of the conditional branch instruction, and a signal 18 urges the restart of the pushup storage instruction according to a program counter and generates a signal 19 requesting a new instruction stream.
JP4016181A 1981-03-19 1981-03-19 Pipeline computer Pending JPS57153342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4016181A JPS57153342A (en) 1981-03-19 1981-03-19 Pipeline computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4016181A JPS57153342A (en) 1981-03-19 1981-03-19 Pipeline computer

Publications (1)

Publication Number Publication Date
JPS57153342A true JPS57153342A (en) 1982-09-21

Family

ID=12573030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4016181A Pending JPS57153342A (en) 1981-03-19 1981-03-19 Pipeline computer

Country Status (1)

Country Link
JP (1) JPS57153342A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01500066A (en) * 1986-01-29 1989-01-12 ディジタル　エクイプメント　コ−ポレ−ション Methods for implementing the Branch Directive
JPH03129441A (en) * 1989-06-20 1991-06-03 Fujitsu Ltd Branch instruction execution device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01500066A (en) * 1986-01-29 1989-01-12 ディジタル　エクイプメント　コ−ポレ−ション Methods for implementing the Branch Directive
JPH0350295B2 (en) * 1986-01-29 1991-08-01 Digital Equipment Corp
JPH03129441A (en) * 1989-06-20 1991-06-03 Fujitsu Ltd Branch instruction execution device

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