JPH04142081A - Mos transistor - Google Patents

Abstract

PURPOSE:To lower the probability that a grain border arrives at the bottom of a gate from the tip of said gate and prevent the formation of an impurity region in a channel region by setting the gate under multilayer structure. CONSTITUTION:A gate 5 is formed with three layers of polysilicon 51 to 53. As a result, grain borders 71 to 73 arrive at the bottom of the gate from the top in terms of the respective polysilicon 51 to 53, but when the whole gate is considered, they hardly arrive at the bottom from the top. In other words, there is an exceptionally low probability that the grain borders 71 to 73 arriving at the bottom from the top in each layer 51 to 53, are lapped on the entire layer. Therefore, no impurity arrive at a channel region passing through the grain borders. This construction makes it possible to avoid the formation of an impurity region in the channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to MO3I transistors, and in particular to their gate structures.

[Conventional technology]

FIG. 4 is a cross-sectional side view showing the structure of a conventional MOS transistor. A source 2. which is an n-type impurity region is formed on the surface of the p-type silicon substrate 1. A train 3, which is also an n-type impurity region, is provided, and a gate oxide film 4. Furthermore, gate 5 is on top of that.
is provided. As the gate 5, a single layer of polysilicon is usually used.

Next, the operation will be explained. When a positive voltage higher than the threshold voltage is applied to the gate 5, an inversion layer is formed in the channel region 6, the source 2 and the drain 3 are electrically connected, and this MO
The S transistor is turned on.

On the other hand, when the positive voltage of the gate 5 drops below the threshold, the inversion layer of the channel region 6 disappears, the source 2 and the train 3 are electrically isolated, and this MOS transistor becomes OF
F.

In fabricating such a kiO3h transistor, source 2. When forming the drain 3, the keto oxide film 4 is usually
．． After forming the polysilicon gate 5, ions are implanted from the gate 5 side. Ion implantation is not performed under the gate oxide film 4 because it is blocked by the polysilicon gate 5, and the source 2. is an n-type impurity region next to the gate oxide film 4. A drain 3 is formed and a channel region 6 is formed under the gate oxide film 4 which is not ion-implanted.

[Invention or problem to be solved]

The conventional MOS) transistor is constructed as described above, and since the gate 5 is usually a single layer of polysilicon,
There was a problem in that ions were sometimes implanted into the channel region 6 as well.

To explain this with the drawings, in FIG. 5, the gate oxide film 4. When ions are implanted into the p-type silicon substrate 1 on which the polysilicon gate 5 is formed, the grain boundaries 7 existing in the polysilicon gate 5 reach the bottom surface from the top surface of the polysilicon gate 5. , the ion-implanted impurity 9 passes through the grain boundary 7 and reaches below the gate oxide film 4 . Therefore, as shown in FIG. 6, an impurity region 10 is also formed in the channel region 6, causing a problem in that the electrical characteristics of the MOS transistor change.

Furthermore, each grain of polysilicon is a single crystal and has its own crystal direction. Since impurity-implanted ions are easily transmitted in a certain crystal direction, grains are formed in the polysilicon film with a certain probability in a crystal direction that allows impurities to easily pass through.

For example, if there is a grain 12 that easily transmits the ion-implanted impurity 9 as shown in FIG. 8, the ion-implanted impurity 9 will penetrate into the channel region 6 through this grain 12 as shown in FIG. Region 10 is formed,
Another problem was that the electrical characteristics of the MOS transistor changed.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a MOS transistor in which no impurity region 10 is formed in the channel region 6.

[Means to solve the problem]

The MOS transistor according to the present invention has a gate having a multilayer structure of three or more layers.

[Effect]

In the MOS transistor of the present invention, the probability that the grain boundaries extending from the upper surface to the lower surface in each layer of the gate overlap in all layers is extremely low, so that ion-implanted impurities will not reach the channel region through the grain boundaries.

Furthermore, in the MOS transistor of the present invention, the probability that the grains, which are easily permeable to impurities, connect from the upper surface to the lower surface of the gate material is extremely low, so that ion-implanted impurities do not reach the channel region through the grains.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, numerals 1 to 4 are exactly the same as the conventional MOS transistors described above. Gate 5 is made of polysilicon 51,5
It is formed of three layers of 2.53. Grain boundaries 71, 72
．． 73 reaches from the upper surface to the lower surface in each of Porin Rico: 151 52. 53, or hardly reaches from the upper surface to the lower surface of the gate 5 as a whole.

The reason for this will be explained. FIG. 3 is a plan view of gate 5, in which broken lines indicate grain boundaries 71 of polysilicon 51 and solid lines indicate grain boundaries 72 of polysilicon 52, respectively. Grain boundaries 73 of polysilicon 53 are omitted.

Grain boundary 71 and grain boundary 72 always create an intersection point 11, where grain boundary 7 intersects polysilicon 51.52.
Penetrate.

That is, in two layers of polysilicon, there is always a grain boundary 7 that passes through it. However, the probability that the grain boundary 73 of the polysilicon 53, which is not shown in FIG. The probability of its existence is extremely small. Moreover, as the number of polysilicon layers increases, this probability becomes even smaller.

Further, as shown in FIG. 9, the probability that the grains 12 that easily transmit the ion-implanted impurities 9 are connected from the upper surface to the lower surface of the gate 5 is extremely low. Therefore, the ion-implanted impurity 9 hardly ever reaches the channel region 6, thus eliminating the formation of the impurity region 10 and not changing the electrical characteristics of the MOS transistor.

In the above embodiment, the entire multilayer structure is made of polysilicon, but instead of polysilicon 52, a different material such as high melting point silicide may be used.

For example, Mo5iWS1 is used as the high melting point silicide. In this case, since the electrical resistance of high melting point silicide is lower than that of polysilicon, the resistance value of the gate 5 can be lowered to achieve higher speed and lower power consumption of the device. Furthermore, since polysilicon 5153 or high melting point silicide is sandwiched, problems in the manufacturing process such as changes in contact resistance with respect to conventional polysilicon gates do not occur.

Furthermore, as shown in FIG. 2, polysilicon 51°52.5
3 and high melting point silicides 81, 82, and 83 may be alternately multilayered. Polysilicon 51, which increases the number of layers while lowering the resistance value by using high melting point silicide,
52, 53.54 grain boundaries 71, 72, 73.7
The probability that grain boundaries (not shown) of the high-melting point silicides 81, 82, and 83 reach the bottom surface of the gate 5 from the top surface can be further reduced, and the formation of the impurity region 10 can be eliminated.

〔Effect of the invention〕

As described above, according to the present invention, since the gate of the MOS transistor has a multilayer structure of three or more layers, the probability that the grain boundary will reach the bottom surface from the top surface of the gate is extremely low, and the grain boundary that allows impurities to easily pass through the gate The probability of connection from the top surface to the bottom surface is extremely low, and the formation of an impurity region in the channel region due to ion implantation during source and drain formation is prevented, resulting in a MOS with stable electrical characteristics.
This has the effect of a transistor.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional side view of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional side view of a MOS transistor according to another embodiment, and FIG. 3 is a plan view of a gate according to an embodiment of the present invention. , FIG. 4 is a cross-sectional side view of a conventional MOS) transistor, FIGS. 5 to 7 are cross-sectional side views showing problems of the conventional technology, and FIG. 8 is a plan view of a gate showing problems of the conventional technology. FIG. 9 shows a MOS according to an embodiment of the present invention.
FIG. 2 is a cross-sectional side view of a transistor. In the figure, 5 is a gate, 51, 52, 53, 54 are polysilicon, and 81, 82, 83 are high melting point silicides. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 81.82.83 High melting point silicide

Claims (1)

[Claims] (1) MO with a gate consisting of a multilayer structure of three or more layers
S transistor.