JPH04139841A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH04139841A JPH04139841A JP26442990A JP26442990A JPH04139841A JP H04139841 A JPH04139841 A JP H04139841A JP 26442990 A JP26442990 A JP 26442990A JP 26442990 A JP26442990 A JP 26442990A JP H04139841 A JPH04139841 A JP H04139841A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- semiconductor chip
- thin film
- film resistor
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 abstract description 7
- 230000020169 heat generation Effects 0.000 abstract description 6
- 210000004907 gland Anatomy 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 238000005219 brazing Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体パッケージに関し、特にプラスチック
・モールド・パッケージの耐湿性向上に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor packages, and particularly to improving the moisture resistance of plastic mold packages.
従来の半導体パッケージを使用している半導体装置の平
面図の一例を第３図に示す。従来、使用されている半導
体パッケージのリードフレームは、半導体チップ搭載部
３７と内部リート３８を有し、半導体チップ搭載部３７
上に半導体チップ３５をマウント用ロー材３６によって
搭載し、半導体チップ３５上の電極と内部リード３８と
をボンディング用金属線３９で接続し封入樹脂４０で封
入されている。FIG. 3 shows an example of a plan view of a semiconductor device using a conventional semiconductor package. A lead frame of a conventionally used semiconductor package has a semiconductor chip mounting portion 37 and an internal lead 38.
A semiconductor chip 35 is mounted thereon by a mounting brazing material 36, and electrodes on the semiconductor chip 35 and internal leads 38 are connected with bonding metal wires 39 and sealed with an encapsulating resin 40.
この従来の半導体パッケージを使用しているプラスチッ
ク・モールド・パッケージは、ハーメチックシールパッ
ケージと比較して、不純物を含む水分の侵入による半導
体チップの電気的特性劣化及び電極腐食によるホンディ
ング用金属線の開放・短絡等、高温高湿度環境における
故障モードが多いという問題点があった。Compared to hermetically sealed packages, plastic molded packages that use this conventional semiconductor package are more susceptible to deterioration of the electrical characteristics of the semiconductor chip due to the ingress of moisture containing impurities and to the opening of the metal wire for bonding due to electrode corrosion. - There was a problem that there were many failure modes such as short circuits in high temperature and high humidity environments.
本発明の半導体パッケージは、リードフレーム内の内部
リードの中間部または半導体チップ搭載部の全体を取り
囲んでいる薄膜抵抗体から成る枠型を有し、半導体チッ
プの電源用パッド及びグランド用パッドにボンディング
用金属線にて接続されている内部リードと前記枠型とを
ボンディング用金属線にて接続されていることを特徴と
する。The semiconductor package of the present invention has a frame made of a thin film resistor that surrounds the entire middle part of the internal leads in the lead frame or the semiconductor chip mounting area, and is bonded to the power pad and ground pad of the semiconductor chip. The internal lead, which is connected by a metal wire for bonding, and the frame mold are connected by a metal wire for bonding.
前記半導体パッケージを使用して組立完了した半導体装
置を実装し、バイアスが半導体装置に供給されると、半
導体装置に使用している半導体チップが正常に機能する
と同時に、薄膜抵抗体から成る枠型による発熱効果によ
り外部からの不純物を含む水分の侵入を防ぎ、耐湿性の
向上をはかることができる。When the assembled semiconductor device is mounted using the semiconductor package and a bias is supplied to the semiconductor device, the semiconductor chip used in the semiconductor device functions normally, and at the same time, the frame mold made of the thin film resistor The heat generation effect prevents moisture containing impurities from entering from the outside and improves moisture resistance.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の半導体パッケージを使用した半導体
装置の第１の実施例の平面図である。本実施例の半導体
パッケージは、リードフレーム内の内部リード６の中間
部の周囲全体を取り囲んでいる薄膜抵抗体から成る枠型
９を有し、マウント用ロー材２により半導体チップ搭載
部３にマウントされた半導体チップ１の電源用パット４
及びクランド用パッド５にボンティング用金属線１２，
１３にて接続する。FIG. 1 is a plan view of a first embodiment of a semiconductor device using the semiconductor package of the present invention. The semiconductor package of this embodiment has a frame 9 made of a thin film resistor that surrounds the entire middle part of the internal lead 6 in the lead frame, and is mounted on the semiconductor chip mounting section 3 using a mounting brazing material 2. power supply pad 4 of semiconductor chip 1
and bonding metal wire 12 to the gland pad 5,
Connect at 13.
組立完了した半導体装置にバイアスを供給すると、半導
体装置に使用している半導体チップ１が正常に機能する
と同時に、薄膜抵抗体から成る枠型９による発熱効果に
より、外部からの不純物を含む水分１４．１５の侵入を
防ぐことが可能になる。When bias is supplied to the assembled semiconductor device, the semiconductor chip 1 used in the semiconductor device functions normally, and at the same time, the heat generation effect of the frame 9 made of a thin film resistor removes moisture 14 containing impurities from the outside. It becomes possible to prevent the intrusion of 15 people.
第２図は、本発明の第２の実施例の平面図である。本実
施例の半導体パッケージは、リードフレーム内の半導体
チップ搭載部１９の周囲全体を取り囲んでいる薄膜抵抗
体から成り、かつ、ホンディング可能領域を２カ所もち
、それ以外は表面が電気的絶縁物てコーティングされて
いる枠型２４を有し、マウント用ロー材１８によって半
導体チップ搭載部９にマウントされた半導体デツプ１７
の電源用パッド２０及びグランド用パッド２１にボンデ
インク用金属線２６．２７にて接続されている内部リー
ド２２．２３と前記枠型２４のボンディング可能領域と
をボンディング用金属線２８．２９にて接続する。FIG. 2 is a plan view of a second embodiment of the invention. The semiconductor package of this embodiment consists of a thin film resistor that surrounds the entire periphery of the semiconductor chip mounting part 19 in the lead frame, and has two areas where bonding is possible, and the surface of the other parts is made of electrically insulating material. The semiconductor dip 17 has a frame 24 coated with a metal oxide and is mounted on the semiconductor chip mounting portion 9 with a mounting brazing material 18.
The internal leads 22.23, which are connected to the power supply pad 20 and the ground pad 21 by bonding ink metal wires 26.27, are connected to the bondable area of the frame 24 by bonding metal wires 28.29. do.
組立完了した半導体装置にバイアスを供給すると、半導
体装置に使用している半導体チップ１−７が正常に機能
すると同時に、枠型２４による発熱効果により、外部か
らの不純物を含む水分３２゜３３の侵入を防ぐことが可
能になる。また、半導体チップ１７上の電極と内部リー
ド３１を、接続しているボンティング用金属線３０が変
形しても、枠型２４の表面が電気的絶縁物でコーディン
グされていることから、電気的特性不良を容易に回避で
きる。When bias is supplied to the assembled semiconductor device, the semiconductor chips 1-7 used in the semiconductor device function normally, and at the same time, the heat generation effect of the frame 24 prevents moisture 32, 33 containing impurities from entering from outside. It becomes possible to prevent Furthermore, even if the bonding metal wire 30 connecting the electrode on the semiconductor chip 17 and the internal lead 31 is deformed, the surface of the frame 24 is coated with an electrical insulator, so that the electrical Characteristic defects can be easily avoided.
以上説明したように本発明は、リードフレーム内の内部
リードの中間部、または半導体チップ搭載部の全体を取
り囲んでいる薄膜抵抗体から成る枠型を有し、半導体チ
ップの電源用パッド及びグランド用パッドにボンディン
グ用金属線にて接続されている内部リードと枠型とをボ
ンディング用金属線にて接続する構造にしなので、本発
明の半導体パッケージを使用して組立完了した半導体装
置にバイアスを供給すると、半導体装置に使用している
半導体チップが正常に機能すると同時に、薄膜抵抗体か
ら成る枠型による発熱効果により、外部からの不純物を
含む水分の侵入を防ぎ、耐湿性の向上をはかれるという
効果を有する。As explained above, the present invention has a frame made of a thin film resistor that surrounds the middle part of the internal leads in the lead frame or the entire semiconductor chip mounting area, and is used for power supply pads and ground of the semiconductor chip. Since the internal lead, which is connected to the pad by the metal wire for bonding, and the frame are connected by the metal wire for bonding, it is possible to supply a bias to the semiconductor device assembled using the semiconductor package of the present invention. At the same time, the semiconductor chips used in semiconductor devices function properly, and the heat generation effect of the frame made of thin film resistors prevents the intrusion of moisture containing impurities from the outside, improving moisture resistance. have
第１図は本発明の第１の実施例の半導体パッケージを使
用した半導体装置の平面図、第２図は、本発明の第２の
実施例の半導体パッケージを使用した半導体装置の平面
図、第３図は、従来の半導体パッケージを使用した半導
体装置の平面図である。
１．１７・・半導体デツプ、２，１８・・・マウント用
ロー材、３，１つ・半導体チップ搭載部、４゜２０・・
・電源用パッド、５．２１・・グランド用パッド、６，
７．８，２２．２３ ・内部リード、９２４・・薄膜
抵抗体からなる枠型、１０．１１．１２．１．３，２６
，２７．２８．２９・・・ボンデインク用金属線、１４
，１５，３２．３３・・・不純物を含む水分、１．６．
３４・・・封入樹脂、３０・・・変形したホンティング
線。FIG. 1 is a plan view of a semiconductor device using a semiconductor package according to a first embodiment of the present invention, and FIG. 2 is a plan view of a semiconductor device using a semiconductor package according to a second embodiment of the present invention. FIG. 3 is a plan view of a semiconductor device using a conventional semiconductor package. 1.17... Semiconductor depth, 2, 18... Mounting brazing material, 3, 1. Semiconductor chip mounting part, 4°20...
・Power supply pad, 5.21...Ground pad, 6,
7.8, 22.23 ・Internal lead, 924...Frame type made of thin film resistor, 10.11.12.1.3, 26
, 27.28.29... Metal wire for bonde ink, 14
, 15, 32.33... Moisture containing impurities, 1.6.
34... Encapsulating resin, 30... Deformed Honting wire.
Claims (1)
チップ搭載部の全体を取り囲んでいる薄膜抵抗体から成
る枠型を有し、半導体チップの電源用パッド及びグラン
ド用パッドにボンディング用金属線にて接続されている
内部リードと前記枠型とをボンディング用金属線にて接
続されていることを特徴とする半導体パッケージ。It has a frame shape made of a thin film resistor that surrounds the middle part of the internal leads in the lead frame or the entire semiconductor chip mounting area, and is connected to the power supply pad and ground pad of the semiconductor chip with a metal wire for bonding. A semiconductor package characterized in that the internal leads and the frame are connected by a bonding metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26442990A JPH04139841A (en) | 1990-10-01 | 1990-10-01 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26442990A JPH04139841A (en) | 1990-10-01 | 1990-10-01 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04139841A true JPH04139841A (en) | 1992-05-13 |
Family
ID=17403064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26442990A Pending JPH04139841A (en) | 1990-10-01 | 1990-10-01 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04139841A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150140828A (en) | 2013-04-15 | 2015-12-16 | 고꾸리쯔다이가꾸호오진 구마모또 다이가꾸 | Fire-resistant magnesium alloy and production method therefor |
-
1990
- 1990-10-01 JP JP26442990A patent/JPH04139841A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150140828A (en) | 2013-04-15 | 2015-12-16 | 고꾸리쯔다이가꾸호오진 구마모또 다이가꾸 | Fire-resistant magnesium alloy and production method therefor |
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