JPH027447A - Resin-sealed type semiconductor device - Google Patents
Resin-sealed type semiconductor deviceInfo
- Publication number
- JPH027447A JPH027447A JP63157343A JP15734388A JPH027447A JP H027447 A JPH027447 A JP H027447A JP 63157343 A JP63157343 A JP 63157343A JP 15734388 A JP15734388 A JP 15734388A JP H027447 A JPH027447 A JP H027447A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- contact
- region
- wiring part
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005538 encapsulation Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 230000007797 corrosion Effects 0.000 abstract description 7
- 238000005260 corrosion Methods 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 7
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 244000171726 Scotch broom Species 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に関し、特にボンディン
グパッドと金属配線との接続構造を改良した樹脂封止型
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device with an improved connection structure between bonding pads and metal wiring.
従来、樹脂封止型半導体装置は、そのパッケージング方
法が量産性に優れていることにより、パッケージングコ
ストが安価になり、このため多くの品種の半導体装置に
適用されていた。Conventionally, resin-sealed semiconductor devices have been applied to many types of semiconductor devices because their packaging method has excellent mass productivity, resulting in low packaging costs.
しかしながら、この種の半導体装置の外周囲を覆う樹脂
体自体は耐湿性が不十分であるとともに、外周囲に樹脂
割れを起してその割れから水分が侵入したり、あるいは
樹脂体から外部に突出する外部リードと樹脂との界面か
ら水分が侵入するといったことが発生しやすかった。い
ずれにしても、この樹脂封止型半導体装置は耐水性がな
いという問題がある。この水分が侵入するという問題は
、やがては、パッシベーション膜から露出したボンディ
ングパッドの領域に腐食を引起し、ついには、腐食部分
が電気的に断線することである。この腐食防止方法とし
て従来は、主として、パッケージの材料、外部リードと
樹脂との界面の構造の改良、及び半導体チップ面のパッ
シベーション膜の改良等を施すといった改善策がとられ
ていた。However, the resin body itself that covers the outer periphery of this type of semiconductor device has insufficient moisture resistance, and the resin may crack around the outer periphery, allowing moisture to enter through the cracks, or may protrude from the resin body to the outside. It was easy for moisture to enter from the interface between the external lead and the resin. In any case, this resin-sealed semiconductor device has a problem in that it is not water resistant. The problem with this moisture infiltration is that it eventually causes corrosion in the area of the bonding pad exposed from the passivation film, and eventually the corroded portion becomes electrically disconnected. Conventionally, methods for preventing this corrosion have mainly been taken by improving the material of the package, the structure of the interface between the external leads and the resin, and improving the passivation film on the surface of the semiconductor chip.
上述した従来の樹脂封止型半導体装置の改善では、樹脂
自体の耐湿性が完全無欠という樹脂材料はなく、外部リ
ードと樹脂との界面を改善しても、水分は樹脂層内に侵
入する。また、半導体チップ面にパッシベーション膜を
形成しても、ボンディングパッド上にはパッシベーショ
ン膜を形成することが出来ないので、この露出した部分
の腐食は避けられないという問題がある。 本発明の目
的は腐食が起きても、より長時間に電気的断線を起さな
い樹脂封止型半導体装置を提供することにある。In the improvement of the conventional resin-sealed semiconductor device described above, there is no resin material whose resin itself has perfect moisture resistance, and even if the interface between the external lead and the resin is improved, moisture still infiltrates into the resin layer. Further, even if a passivation film is formed on the surface of the semiconductor chip, the passivation film cannot be formed on the bonding pad, so there is a problem that corrosion of this exposed portion is unavoidable. An object of the present invention is to provide a resin-sealed semiconductor device that does not cause electrical disconnection for a longer period of time even if corrosion occurs.
本発明の樹脂封止型半導体装置は、半導体基板の一主面
上に形成された半導体素子と、前記半導体素子上に配置
された層間絶縁膜を介して配置された前記半導体素子と
ボンディングパッドとを接続する金属配線とを有する樹
脂封止型半導体装置において、前記半導体基板の一主面
上と前記層間絶縁膜との間に配置され前記ボンディング
パッドに対応する領域で前記金属配線と接続されるとと
もに前記ボンディングパッドに対応する領域以外で前記
金属配線と接続される導電層とを含んで構成される。The resin-sealed semiconductor device of the present invention includes a semiconductor element formed on one main surface of a semiconductor substrate, and a bonding pad and the semiconductor element arranged through an interlayer insulating film arranged on the semiconductor element. in a resin-sealed semiconductor device having a metal wiring that connects the metal wiring, which is arranged between one main surface of the semiconductor substrate and the interlayer insulating film and connected to the metal wiring in a region corresponding to the bonding pad. and a conductive layer connected to the metal wiring in a region other than the region corresponding to the bonding pad.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明による第１の実施例を説明するための半
導体チップの部分平面図、第２図は第１図のＸＸ断面図
である。同図に示すように、この樹脂封止型半導体装置
は本発明の主旨である半導体チップの一部分の改造につ
いてのみ示している。FIG. 1 is a partial plan view of a semiconductor chip for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view XX of FIG. 1. As shown in the figure, this resin-sealed semiconductor device shows only the modification of a portion of the semiconductor chip, which is the gist of the present invention.
すなわち、従来は実施されなかった導電層である多結晶
シリコン層２を半導体基板９の上に形成された酸化膜８
上に設けることである。勿論、この多結晶シリコン層２
の上には、従来の構造と同じように、層間絶縁膜７とア
ルミニウムの金属配線１ｂ及びこの配線と一体に形成さ
れる金属パッドであるボンディングパッド１ａが形成さ
れ、ボンディングパッド１ａの領域を除いた表面を保護
用のパッシベーション膜５で覆うようになっている。That is, a polycrystalline silicon layer 2, which is a conductive layer, which has not been implemented in the past, is replaced by an oxide film 8 formed on a semiconductor substrate 9.
It is to be placed on top. Of course, this polycrystalline silicon layer 2
Similar to the conventional structure, an interlayer insulating film 7, an aluminum metal wiring 1b, and a bonding pad 1a, which is a metal pad formed integrally with this wiring, are formed on the top, except for the area of the bonding pad 1a. The exposed surface is covered with a protective passivation film 5.
ここで、前述の多結晶シリコン層２の大きさは、第２図
に示すように、ボンディングパッド１ａと金属配線１ｂ
の一部を含めた領域と同程度かあるいはやや小いさめに
形成する。また、この多結晶シリコン層２は金属配線１
ｂの領域とボンディングパッド１ａの領域で、それぞれ
に第２のコンタクト６と第１のコンタクｌ−４で接続さ
れている。Here, the size of the above-mentioned polycrystalline silicon layer 2 is as shown in FIG.
It is formed to be the same size or slightly smaller than the area including a part of the area. Moreover, this polycrystalline silicon layer 2 is
The region b and the region of the bonding pad 1a are connected to each other by a second contact 6 and a first contact 1-4, respectively.
次に、この半導体チップの構造の改良によってもたらす
機能の向上を説明する。例えば、今、金属細線１０ある
いは樹脂体（図示せず）を経て水分が侵入したとすると
、まず、ボンディングボール３の周囲の露出したボンデ
ィングパッド１ａの領域のアルミニウムの金属配線が腐
食し始める。Next, the improved functionality brought about by improving the structure of this semiconductor chip will be explained. For example, if moisture enters through the thin metal wire 10 or the resin body (not shown), first the aluminum metal wiring in the exposed bonding pad 1a area around the bonding ball 3 begins to corrode.
通常、この金属配線の厚さは横方向の寸法に比し極端に
薄いため、まず、腐食は金属配線の底面に到達し、やが
ては、ボンディングボール３の周囲が断線すると考えら
れる。しかし、仮にこの断線が起きても、第１のコンタ
クト４と第２のコンタクト６を通して導通がとれている
ため、直ちに電気的断線不良とはならない。Since the thickness of this metal wiring is usually extremely thin compared to its lateral dimension, it is thought that the corrosion will first reach the bottom surface of the metal wiring, and eventually the area around the bonding ball 3 will be disconnected. However, even if this disconnection occurs, conduction is maintained through the first contact 4 and the second contact 6, so it does not immediately become an electrical disconnection defect.
第３図は本発明による第２の実施例を説明するための半
導体チップの部分平面図である。この実施例は、同図に
示すように、第１の実施例に、更に第３のコンタクト１
１を追加したものである。FIG. 3 is a partial plan view of a semiconductor chip for explaining a second embodiment of the present invention. As shown in the figure, this embodiment has a third contact 1 in addition to the first embodiment.
1 has been added.
この第３のコンタクト１１は第１のコンタクト４の周囲
を囲むように形成されているので、ボンディングボール
３の周囲のパッシベーション膜５がら露出したアルミニ
ウムのボンディングパッドの領域の金属配線厚さに、第
３のコンタクト１１の厚さと多結晶シリコン層２の厚さ
を加えたと同様の厚さとなる。従って、この実施例の半
導体チップは電気的断線に至る時間が、第１の実施例に
比べより長くなるという利点がある。Since the third contact 11 is formed so as to surround the first contact 4, the thickness of the metal wiring in the area of the aluminum bonding pad exposed through the passivation film 5 around the bonding ball 3 has a third contact. The thickness is the same as the sum of the thickness of the contact 11 of No. 3 and the thickness of the polycrystalline silicon layer 2. Therefore, the semiconductor chip of this embodiment has the advantage that the time required for electrical disconnection to occur is longer than that of the first embodiment.
以上箱１及び第２の実施例について説明したが、これら
のコンタクト形状及び大きさに限定することはなく、例
えば、ボンデインパッド領域の下部の層間絶縁膜を無く
してボンディング領域と同じ大きさの領域及びボンディ
ングパッド領域と隣接する金属配線の領域とで、これら
ボンディングパッド及び金属配線に対応する導電層でな
る多結晶シリコン層の領域とを接続するれば良いことに
なる。Although Box 1 and the second embodiment have been described above, the shape and size of the contact are not limited to these. It is sufficient to connect the regions of the polycrystalline silicon layer, which is a conductive layer, corresponding to the bonding pads and the metal wires to the region of the metal wiring adjacent to the region and the bonding pad region.
以上説明したように本発明は、ボンディングパッドの下
部に金属配線と導電層である多結晶シリコン層を層間絶
縁膜を介して設けるとともに、ボンディングパッドの下
部に導電層と接続するコンタクトと冗長配線である金属
配線と導電層とを接続するコンタクトを設けたので、水
分が侵入して腐食が起きても、より長時間に電気的断線
を起さない樹脂封止型半導体装置が得られるという効果
がある。As explained above, the present invention provides metal wiring and a polycrystalline silicon layer as a conductive layer under the bonding pad via an interlayer insulating film, and also provides contacts and redundant wiring under the bonding pad to connect to the conductive layer. Since a contact is provided to connect a certain metal wiring and a conductive layer, it is possible to obtain a resin-sealed semiconductor device that does not cause electrical disconnection for a longer period of time even if moisture enters and corrosion occurs. be.
施例を説明するための半導体チップの部分平面図である
。FIG. 2 is a partial plan view of a semiconductor chip for explaining an example.
１ａ・・・ボンディングパッド、１ｂ・・・金属配線、
２・・・多結晶シリコン層、３・・・ボンディングボー
ル、４・・・第１のコンタクト、５・・・パッシベーシ
ョン膜、６・・・第２のコンタクト、７・・・層間絶縁
膜、８・・・酸化膜、９・・・半導体基板、１０・・・
金属細線、１１・・・第３のコンタクト。1a... bonding pad, 1b... metal wiring,
2... Polycrystalline silicon layer, 3... Bonding ball, 4... First contact, 5... Passivation film, 6... Second contact, 7... Interlayer insulating film, 8 ...Oxide film, 9...Semiconductor substrate, 10...
Fine metal wire, 11...Third contact.
第１図は本発明による第１の実施例を説明するための半
導体チップの部分平面図、第２図は第１図のＸＸ断面図
、第３図は本発明による第２の実Ｉａ：ボンテ１ングパ
・ソＥ゛
３・ポンプ□ンゲポー１し
４°箒１のコンタクト
５、パ・ンシベーション月莫
６％２のコンタクト
１０金属細線
７１第３のコンタクト
第 １ 区
第
図FIG. 1 is a partial plan view of a semiconductor chip for explaining a first embodiment of the present invention, FIG. 2 is a XX sectional view of FIG. 1 Ngpa SoE゛3 Pump □ Ngepo 1 and 4° Broom 1 Contact 5, Pa Insivation Month Mo 6% 2 Contact 10 Fine Metal Wire 71 3rd Contact 1st Ward Diagram
Claims (1)
半導体素子上に配置された層間絶縁膜を介して配置され
た前記半導体素子とボンディングパッドとを接続する金
属配線とを有する樹脂封止型半導体装置において、前記
半導体基板の一主面上と前記層間絶縁膜との間に配置さ
れ前記ボンディングパッドに対応する領域で前記金属配
線と接続されるとともに前記ボンディングパッドに対応
する領域以外で前記金属配線と接続される導電層を有す
ることを特徴とする樹脂封止型半導体装置。A resin encapsulation having a semiconductor element formed on one principal surface of a semiconductor substrate, and a metal wiring connecting the semiconductor element and bonding pads arranged through an interlayer insulating film arranged on the semiconductor element. type semiconductor device, which is disposed between one main surface of the semiconductor substrate and the interlayer insulating film, is connected to the metal wiring in a region corresponding to the bonding pad, and is connected to the metal wiring in a region other than the region corresponding to the bonding pad. A resin-sealed semiconductor device characterized by having a conductive layer connected to metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63157343A JPH027447A (en) | 1988-06-24 | 1988-06-24 | Resin-sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63157343A JPH027447A (en) | 1988-06-24 | 1988-06-24 | Resin-sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH027447A true JPH027447A (en) | 1990-01-11 |
Family
ID=15647610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63157343A Pending JPH027447A (en) | 1988-06-24 | 1988-06-24 | Resin-sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH027447A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10328982B2 (en) | 2010-12-14 | 2019-06-25 | Camso Inc. | Drive sprocket, drive lug configuration and track drive arrangement for an endless track vehicle |
-
1988
- 1988-06-24 JP JP63157343A patent/JPH027447A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10328982B2 (en) | 2010-12-14 | 2019-06-25 | Camso Inc. | Drive sprocket, drive lug configuration and track drive arrangement for an endless track vehicle |
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