JPH04139738A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04139738A JPH04139738A JP26268090A JP26268090A JPH04139738A JP H04139738 A JPH04139738 A JP H04139738A JP 26268090 A JP26268090 A JP 26268090A JP 26268090 A JP26268090 A JP 26268090A JP H04139738 A JPH04139738 A JP H04139738A
- Authority
- JP
- Japan
- Prior art keywords
- defective
- semiconductor
- semiconductor chip
- mark
- sorting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 230000002950 deficient Effects 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims description 7
- 235000012431 wafers Nutrition 0.000 abstract description 16
- 238000005259 measurement Methods 0.000 abstract description 10
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 235000015278 beef Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
り粟上旦科里分■
本発明は、半導体装置の製造方法に関し、特に半導体ウ
ェーハに形成された半導体チップの電気的特性を検査し
、検査結果に応じてマークを付し、このマークの有無に
より選別する方法に関する。[Detailed Description of the Invention] Riwakami Danka Ribun■ The present invention relates to a method for manufacturing a semiconductor device, and in particular, to inspecting the electrical characteristics of a semiconductor chip formed on a semiconductor wafer and attaching marks according to the inspection results. , relates to a method of sorting based on the presence or absence of this mark.
従来旦皮斂
従来、半導体チップの選別では電気的特性検査装置によ
り、良、不良を判定し、第２図に示すように良品半導体
チップ２ａにはインク、レーザ等の不良マーク３を形成
せず、表面はそのままの杖態とし、不良半導体チップ２
ｃには不良マーク３を形成している。Conventionally, when sorting semiconductor chips, an electrical property inspection device is used to determine whether they are good or bad, and as shown in FIG. , the surface remains as it is, and the defective semiconductor chip 2
A defective mark 3 is formed at c.
ところで、上記の従来の半導体チップの選別では電気的
特性検査装置の測定針の接触圧不足等に起因する誤測定
により、第２図に示すように良品半導体チップ２ｂに不
良マーク３を形成する場合があるので、不良マーク３が
形成された良品半導体チップ２ｂは、二度と良品とは選
別できずムダになってしまうという問題があった。By the way, in the above-mentioned conventional semiconductor chip sorting, there are cases where a defective mark 3 is formed on a non-defective semiconductor chip 2b as shown in FIG. Therefore, there is a problem that the non-defective semiconductor chips 2b on which the defect mark 3 has been formed cannot be classified as non-defective products again and are wasted.
、の
本発明は、上記の課題を解決するために、半導体ウェー
ハに形成された半導体チップを電気的特性検査装置によ
り測定する工程と、良品半導体チップにマークする工程
とを設けたことを特徴とする。In order to solve the above-mentioned problems, the present invention is characterized by providing a step of measuring semiconductor chips formed on a semiconductor wafer with an electrical property testing device, and a step of marking non-defective semiconductor chips. do.
赳
上記の工程によると、電気的特性検査装■の測定により
、良品と判定された半導体チップにマークすることによ
り、電気的特性検査装置の誤測定で不良となった半導体
チップにはマークされないため、正確な再測定を行い良
品と判定すればマークを形成することにより、−度不良
と選別された半導体チップを良品として選別することが
できる。According to the above process, by marking semiconductor chips determined to be non-defective by measurement using the electrical property testing equipment, semiconductor chips that are found to be defective due to incorrect measurements by the electrical property testing equipment will not be marked. If accurate re-measurement is performed and the semiconductor chip is determined to be non-defective, a mark is formed on the semiconductor chip, so that the semiconductor chip that has been selected as defective can be selected as non-defective.
尖息阻
以下、この発明の実施例について図面を参照して説明す
る。Embodiments of the present invention will now be described with reference to the drawings.
第１図は本発明の一実施例方法について説明する半導体
ウェーハの平面図である。図において４ａは１回選別後
の半導体ウェーハ、４ｂは再選別後の半導体ウェーハ、
５ａは１回目の選別後良品マークされた良品半導体チッ
プ、５ｂは１回目の選別で誤選別により良品マークされ
なかった良品半導体チップ、５ｃは１回選別後も再選別
後も不良と選別され、良品マークされなかった不良半導
体チップ、６ａは１回選別後も再選別後も良品と選別さ
れ良品マークされた良品半導体チップ、６ｂは１回目の
選別後、誤選別により良品マークされず再測定により良
品として選別され良品マークされた良品半導体チップ、
７は良品として選別された半導体チップに形成された良
品マークである。FIG. 1 is a plan view of a semiconductor wafer for explaining one embodiment of the method of the present invention. In the figure, 4a is a semiconductor wafer after one-time sorting, 4b is a semiconductor wafer after re-sorting,
5a is a non-defective semiconductor chip that was marked as good after the first sorting, 5b is a good semiconductor chip that was not marked as good due to erroneous sorting in the first sorting, 5c is a good semiconductor chip that was selected as defective both after the first sorting and after re-sorting, Defective semiconductor chips that were not marked as non-defective. 6a are non-defective semiconductor chips that were selected as non-defective and marked as non-defective both after the first sorting and re-sorting. 6b is a non-defective semiconductor chip that was not marked as non-defective after the first sorting due to incorrect sorting and was remeasured. Non-defective semiconductor chips that have been selected and marked as non-defective,
7 is a non-defective mark formed on a semiconductor chip selected as a non-defective product.
良品マーク７の種類はインクである。The type of non-defective mark 7 is ink.
本発明では半導体ウェーハを電気的特性検査装置で測定
し、良品と判定された半導体チップに良品マーク７を形
成するので、例えば電気的特性検査装置による測定が不
安定な状態で選別を行ったために、良品であるのに良品
マークが形成されなかった良品半導体チップ５ｂができ
た場合でも、電気的特性検査装置による測定が安定した
状態で再選別を行えば、１回目の選別で不良となり、良
品マークされなかった良品半導体チップ５ｂは良品マー
ク７を形成されて良品半導体チップ６ｂとなり、良品と
して扱うことができるので、電気的特性検査装置の誤測
定による半導体ウェーハの良品率低下を防ぐという効果
がある。In the present invention, semiconductor wafers are measured with an electrical property testing device, and a non-defective mark 7 is formed on semiconductor chips determined to be non-defective. Even if a non-defective semiconductor chip 5b with no non-defective mark is produced, if it is re-sorted after the measurement by the electrical property testing device is stable, it will be defective in the first sorting and the non-defective product will be rejected. The unmarked non-defective semiconductor chip 5b has a non-defective mark 7 formed thereon and becomes a non-defective semiconductor chip 6b, and can be treated as a non-defective semiconductor chip. This has the effect of preventing a decline in the non-defective rate of semiconductor wafers due to erroneous measurements by the electrical property inspection device. be.
良品マーク７に用いるインクには、例えばフェノールイ
ンクを用い、マークする位置は半導体チップ内でポンデ
ィングパッドのない部分とすれば、組立工程ではワイヤ
のボンディング作業性が悪くなるなどの諸問題はなく、
組立後の半導体装置の電気的特性は従来の不良マークの
ない良品半導体チップを組立てた半導体装置の電気的特
性と差がない。For example, if phenol ink is used as the ink used for the non-defective product mark 7, and if the mark is placed on a part of the semiconductor chip where there is no bonding pad, there will be no problems such as poor wire bonding workability during the assembly process. ,
The electrical characteristics of the assembled semiconductor device are the same as those of a semiconductor device assembled from conventional non-defective semiconductor chips without defective marks.
髪肌立処果
以上説明したように、この発明は良品半導体チップにマ
ークすることにより、電気的特性検査装置の誤測定のた
めにいったん不良と選別された良品半導体チップを、再
選別により良品半導体チップとして選別できるので、電
気的特性検査装置の誤測定による半導体ウェーハ良品率
低下を防ぐことができるという効果がある。As explained above, the present invention marks non-defective semiconductor chips, so that non-defective semiconductor chips that have been once sorted out as defective due to erroneous measurements by an electrical property testing device can be re-sorted to become non-defective semiconductor chips. Since the semiconductor wafers can be sorted as chips, it is possible to prevent a decrease in the yield of semiconductor wafers due to erroneous measurements by the electrical property testing device.
第１図は本発明により選別された半導体ウェーハマツプ
、第２図は従来の半導体チップ選別方法により選別され
た半導体ウェーハマツプである。
１・・・・・・半導体ウェーハ、
２ａ・・・・・・良品半導体チップ、
２ｂ・・・・・・不良マークされた良品半導体チップ、
２ｃ・・・・・・不良半導体チップ、
３・・・・・・不良マーク、
４ａ・・・・・・半導体ウェーハ（１回選別後）、４ｂ
・・・・・・半導体ウェーハ（再選別後）、５ａ・・・
・・・良品半導体チップ、
５ｂ・・・・・・良品マークされなかった良品半導体チ
ップ、
５ｃ・・・・・・不良半導体チップ、
６ａ・・・・・・良品半導体チップ、
６ｂ・・・・・・良品半導体チップ、
７・・・・・・良品マーク。
第
図
第
図
４ユ、を参体７Ｉ−ハ（ＩＷ：Ｊ還号Ｊ改）４ｂ、千１
／−抹ｍ−ハ（＾還別１灸）５ａ劇晶〒膚り情しテツフ
。
ｓｂ、 ＊ｒｏマー７されｑｐ寡−寥〉牛褥シレ→ブ５
ｃ 不＆亨導心卜一トフ７゜
６α、１ｉｌｊ−マ＃−４本子・７フ
６ｂ ＊：ら千４１体チゾフ。
７ 良品７−７
］、 ！４抹ツェー２．
２α １良、：ａ′Ｆ導硬フフ″
２ｂ、 Ｑｖ−７２ａｒ−ｉ：ａｍａブトブー・フプ
２ｃ、 不良１４＋、ソフ゛
３・不奴７−７FIG. 1 shows a semiconductor wafer map sorted according to the present invention, and FIG. 2 shows a semiconductor wafer map sorted by a conventional semiconductor chip sorting method. 1...Semiconductor wafer, 2a...Good semiconductor chip, 2b...Good semiconductor chip marked as defective,
2c: Defective semiconductor chip, 3: Defective mark, 4a: Semiconductor wafer (after one sorting), 4b
...Semiconductor wafer (after re-sorting), 5a...
...Good semiconductor chip, 5b...Good semiconductor chip that was not marked as good, 5c...Defective semiconductor chip, 6a...Good semiconductor chip, 6b... ...Good quality semiconductor chip, 7...Good quality mark. Figure Figure 4 U, Part 7 I-C (IW: J return J modification) 4b, 1,000
/-Mm-Ha (＾Return 1 Moxibustion) 5a Drama Crystal 〒Sadly Tetsuf. sb, *ro mar 7 and qp small - 寥〉Beef sire → bu 5
c Fu&Hyodoshinboichitof7゜6α, 1ilj-Ma#-4honko・7fu6b *:Rasen41 bodies Chizov. 7 Good product 7-7 ], ! 4 Match Tse 2. 2α 1 good, : a'F conductive hard fufu'' 2b, Qv-72ar-i: ama butboo fufu 2c, bad 14+, soft 3, fufu 7-7
Claims (1)
を測定する工程と、良品半導体チップにマークする工程
とを含むことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising the steps of: measuring electrical characteristics of semiconductor chips formed on a semiconductor wafer; and marking non-defective semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26268090A JPH04139738A (en) | 1990-09-28 | 1990-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26268090A JPH04139738A (en) | 1990-09-28 | 1990-09-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04139738A true JPH04139738A (en) | 1992-05-13 |
Family
ID=17379099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26268090A Pending JPH04139738A (en) | 1990-09-28 | 1990-09-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04139738A (en) |
-
1990
- 1990-09-28 JP JP26268090A patent/JPH04139738A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5711848A (en) | Non-product patterned particle test wafer and testing method therefor | |
| JPH04139738A (en) | Manufacture of semiconductor device | |
| US6340604B1 (en) | Contactor and semiconductor device inspecting method | |
| JPS62261139A (en) | Semiconductor device | |
| US4661771A (en) | Method of screening resin-sealed semiconductor devices | |
| JP3093216B2 (en) | Semiconductor device and inspection method thereof | |
| JPS618939A (en) | Semiconductor device | |
| JP3012242B2 (en) | Manufacturing method of semiconductor integrated circuit | |
| JPS61152034A (en) | Wafer prober | |
| JP2634286B2 (en) | Handler device for testing electrical characteristics of semiconductor devices | |
| JPS6164137A (en) | Semiconductor device | |
| JPS615539A (en) | Semiconductor device | |
| JPH0496343A (en) | Semiconductor device | |
| JPH05299466A (en) | Structure of semiconductor chip and manufacture thereof | |
| JPS6228567B2 (en) | ||
| JPH05211219A (en) | Burn-in method of semiconductor storage device | |
| JPS5946417B2 (en) | Defective semiconductor chip display method | |
| JPS61253847A (en) | Highly reliable semiconductor device | |
| JPH05157780A (en) | Resistance element process monitor device | |
| JPH0325948A (en) | Semiconductor integrated circuit | |
| JPH03228345A (en) | Semiconductor chip and inspection of the chip | |
| JPH0666372B2 (en) | Integrated circuit | |
| JPH01265533A (en) | Manufacture of semiconductor device | |
| JP2002124551A (en) | Semiconductor sorting equipment and method | |
| JPH05304192A (en) | Semiconductor wafer and inspection method thereof |