JPH05299466A - Structure of semiconductor chip and manufacture thereof - Google Patents
Structure of semiconductor chip and manufacture thereofInfo
- Publication number
- JPH05299466A JPH05299466A JP4847992A JP4847992A JPH05299466A JP H05299466 A JPH05299466 A JP H05299466A JP 4847992 A JP4847992 A JP 4847992A JP 4847992 A JP4847992 A JP 4847992A JP H05299466 A JPH05299466 A JP H05299466A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- test pads
- pads
- test
- resistance wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体チップ構造および
その製造方法に関し、特にＧａＡｓウエハー上に形成さ
れた半導体チップ表面に、不良識別マークを付けること
ができる半導体チップ構造およびその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip structure and a method of manufacturing the same, and more particularly to a semiconductor chip structure capable of providing a defect identification mark on the surface of a semiconductor chip formed on a GaAs wafer and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、ウエハー上に形成された複数の半
導体チップの良否判定試験を行った結果、不良となった
半導体チップに対しては、チップ表面上に機械的に傷を
付けたり、レーザ光線により傷を付けたりしている。2. Description of the Related Art Conventionally, as a result of a quality judgment test of a plurality of semiconductor chips formed on a wafer, a defective semiconductor chip is mechanically scratched on the surface of the chip or a laser beam is applied. It is scratched by the light rays.
【０００３】[0003]
【発明が解決しようとする課題】しかし、高周波特性が
良好なＧａＡｓ半導体チップの場合、ＧａＡｓウエハー
が脆いため、不良チップの表面上に機械的に傷を付けた
ときは、チップを切出すときにウエハー全体が割れてし
まうことがあり、このため良品チップが破損するという
問題点がある。また、レーザ光線により傷を付けたとき
は、砒素が蒸発して人体に有害なガスを発生するばかり
でなく、ＧａＡｓチップ上の配線として使用されている
金が飛散して、傷を付けるべき不良チップのみならず隣
接する良品チップの表面をも汚染してしまうという問題
点がある。However, in the case of a GaAs semiconductor chip having good high-frequency characteristics, the GaAs wafer is fragile. Therefore, when the surface of the defective chip is mechanically scratched, or when the chip is cut out. There is a problem in that the entire wafer may be broken, which causes damage to non-defective chips. Also, when scratched by a laser beam, not only arsenic evaporates to generate a harmful gas to the human body, but also gold used as wiring on the GaAs chip scatters, which is a defect that should be scratched. There is a problem that not only the chip but also the surface of the adjacent non-defective chip is contaminated.
【０００４】本発明の目的は、機械的に傷を付けたり、
レーザ光線により傷を付けたりすることなく、半導体チ
ップ表面に不良識別マークを付けることができる半導体
チップ構造およびその製造方法を提供することにある。The object of the present invention is to mechanically scratch,
It is an object of the present invention to provide a semiconductor chip structure capable of forming a defect identification mark on the surface of a semiconductor chip without damaging it with a laser beam, and a manufacturing method thereof.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体チップ構
造は、半導体チップ表面にボンディングパッドとは別に
設けられる複数のテストパッドと、この複数のテストパ
ッド間に設けられるポリシリ抵抗線とを備えている。ま
た、前記ポリシリ抵抗線の代りに電流により溶断する細
配線を置替えてもよい。The semiconductor chip structure of the present invention comprises a plurality of test pads provided on the surface of the semiconductor chip separately from the bonding pads, and a polysilicon resistance line provided between the plurality of test pads. There is. Further, instead of the poly-silicon resistance wire, a fine wiring that is blown by an electric current may be replaced.
【０００６】このような半導体チップ構造は、半導体チ
ップ表面にボンディングパッドと同時に複数のテストパ
ッドを形成する工程と、前記複数のテストパッド間に抵
抗線を形成する工程とを経て製造される。Such a semiconductor chip structure is manufactured through a step of forming a plurality of test pads at the same time on the surface of the semiconductor chip and a step of forming a resistance line between the plurality of test pads.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００８】図１は本発明の一実施例を示すチップの平
面図であり、ＧａＡｓウエハー上に形成された複数の半
導体チップの１つを示している。FIG. 1 is a plan view of a chip showing an embodiment of the present invention, showing one of a plurality of semiconductor chips formed on a GaAs wafer.
【０００９】半導体チップ表面に設けられた複数のボン
ディングパッド１１は、それぞれ内部回路と接続されて
いる。また、テストパッド１２および１３は、それぞれ
ボンディングパッド１１と同一形状をしており、スルー
ホール１４，１５を介してポリシリ抵抗線１６によって
接続されている。ポリシリ抵抗線１６の線幅は、所定の
抵抗値となるように細くなっている。The plurality of bonding pads 11 provided on the surface of the semiconductor chip are each connected to an internal circuit. The test pads 12 and 13 have the same shape as the bonding pad 11, and are connected by the polysilicon resistance line 16 via the through holes 14 and 15. The line width of the polysilicon resistance wire 16 is narrowed to have a predetermined resistance value.
【００１０】さて、半導体チップの良否判定試験を行う
ときは、複数のボンディングパッド１１およびテストパ
ッド１２，１３にテスタの探針（図示せず）をそれぞれ
接触させる。テスタは、複数のボンディングパッド１１
にそれぞれテスト信号を印加し内部回路の特性を測定し
て良否を判定する。不良と判定した場合は、テストパッ
ド１２，１３間に所定の電流を印加する。ポリシリ抵抗
線１６は、印加された電流によって発熱して変色するの
で、ポリシリ抵抗線１６に沿ったチップ表面の特定部分
に筋状のマークを付けることができる。When conducting a pass / fail judgment test on a semiconductor chip, probe tips (not shown) of a tester are brought into contact with the plurality of bonding pads 11 and the test pads 12 and 13, respectively. The tester has a plurality of bonding pads 11
A test signal is applied to each of them to measure the characteristics of the internal circuit to judge pass / fail. If it is determined to be defective, a predetermined current is applied between the test pads 12 and 13. Since the poly-silicon resistance wire 16 is heated by the applied current and changes its color, a streak-like mark can be attached to a specific portion of the chip surface along the poly-silicon resistance wire 16.
【００１１】なお、ポリシリ抵抗線の代りにアルミニウ
ム等の配線材を使用して細配線を形成し、これに所定の
電流を印加して溶断させても同様な効果が得られる。The same effect can be obtained by forming a fine wiring by using a wiring material such as aluminum instead of the poly-silicon resistance wire, and applying a predetermined current to the thin wiring to melt the wiring.
【００１２】このような半導体チップ構造は、半導体チ
ップ表面にボンディングパッドと同時に複数のテストパ
ッドを形成する工程と、複数のテストパッド間に抵抗線
を形成する工程とを経て容易に製造することができる。Such a semiconductor chip structure can be easily manufactured through a step of forming a plurality of test pads at the same time as bonding pads on the surface of the semiconductor chip and a step of forming a resistance line between the plurality of test pads. it can.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、半導体チ
ップ表面にボンディングパッドとは別にテストパッドを
設け、このテストパッド間をポリシリ抵抗線あるいは細
配線によって接続することにより、半導体チップの良否
判定試験により不良と判定した場合は、テストパッドに
所定の電流を印加してポリシリ抵抗線あるいは細配線を
発熱により変色あるいは溶断させ、チップ表面の特定の
部分に筋状のマークを付けることができる。従って、従
来のように、機械的に傷を付けたことによりウエハーが
割れることはなく、また、レーザ光線により砒素が蒸発
したり、配線材料の金が飛散して表面を汚染するという
こともなく、不良識別マークを付けることができる。As described above, according to the present invention, a test pad is provided on the surface of a semiconductor chip in addition to a bonding pad, and the test pads are connected by a polysilicon resistance wire or a fine wiring to judge whether the semiconductor chip is good or bad. When it is determined to be defective by the test, a predetermined current is applied to the test pad to discolor or melt the polysilicon resistance wire or the thin wiring due to heat generation, and a streak mark can be attached to a specific portion of the chip surface. Therefore, unlike the conventional case, the wafer is not cracked due to mechanical damage, and arsenic is not vaporized by the laser beam, and gold of the wiring material is not scattered to contaminate the surface. , A defect identification mark can be attached.
【００１４】更に、このような半導体チップ構造は、半
導体チップ表面にボンディングパッドと同時に複数のテ
ストパッドを形成する工程と、複数のテストパッド間に
抵抗線を形成する工程とによって容易に製造できる。Further, such a semiconductor chip structure can be easily manufactured by a step of forming a plurality of test pads at the same time as bonding pads on the surface of the semiconductor chip and a step of forming a resistance line between the plurality of test pads.
【図１】本発明の一実施例を示すチップの平面図であ
る。FIG. 1 is a plan view of a chip showing an embodiment of the present invention.
１１ ボンディングパッド １２，１３ テストパッド １６ ポリシリ抵抗線 11 Bonding pad 12, 13 Test pad 16 Polysilicon resistance wire
Claims (3)
とは別に設けられる複数のテストパッドと、この複数の
テストパッド間に設けられるポリシリ抵抗線とを備える
ことを特徴とする半導体チップ構造。1. A semiconductor chip structure comprising: a plurality of test pads provided on the surface of the semiconductor chip separately from the bonding pads; and a polysilicon resistance line provided between the plurality of test pads.
溶断する細配線を置替えてなることを特徴とする請求項
１記載の半導体チップ構造。2. The semiconductor chip structure according to claim 1, wherein a thin wire that is blown by an electric current is replaced in place of the poly-silicon resistance wire.
と同時に複数のテストパッドを形成する工程と、前記複
数のテストパッド間に抵抗線を形成する工程とを有する
ことを特徴とする半導体チップ構造の製造方法。3. A method of manufacturing a semiconductor chip structure, comprising: forming a plurality of test pads at the same time as bonding pads on the surface of a semiconductor chip; and forming a resistance line between the plurality of test pads. .
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7236191 | 1991-09-10 | ||
| JP8356791 | 1991-10-16 | ||
| JP3-72361 | 1991-10-16 | ||
| JP3-83567 | 1991-10-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05299466A true JPH05299466A (en) | 1993-11-12 |
Family
ID=26413492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4847992A Pending JPH05299466A (en) | 1991-09-10 | 1992-03-05 | Structure of semiconductor chip and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05299466A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233140A (en) * | 2018-03-05 | 2019-09-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof and working method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0325948A (en) * | 1989-06-23 | 1991-02-04 | Nec Kyushu Ltd | Semiconductor integrated circuit |
| JPH0376241A (en) * | 1989-08-18 | 1991-04-02 | Mitsubishi Electric Corp | Semiconductor device |
-
1992
- 1992-03-05 JP JP4847992A patent/JPH05299466A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0325948A (en) * | 1989-06-23 | 1991-02-04 | Nec Kyushu Ltd | Semiconductor integrated circuit |
| JPH0376241A (en) * | 1989-08-18 | 1991-04-02 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233140A (en) * | 2018-03-05 | 2019-09-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof and working method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980623 |