JPH0287544A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the evaluation to be accelerated by a method wherein a testing dummy wiring circuit is made on a part of a wafer surface and then the dummy wiring is impressed with a current using probes to evaluate the quality and reliability of a wiring on a semiconductor circuit by the fusing current level thereof. CONSTITUTION:The dimensions (diameter, depth) of contact holes 4 and the dimensions (width, thickness) of Al wiring 5 in a testing dummy wiring circuit (TEG) are specified to be in common with those in the semiconductor circuit formed on a wafer. After formation of the Al wiring, probers (arrow marks A, B) are brought into contact with both terminals 5a, 5b to impress the contact hole TEG with current for measuring the fusing current at that time. When the fusing current level is notably lower than the level decided by the width and thickness of the Al wiring, it can be confirmed that the current is fused at any defective Al coverage part. Through these procedures, the acceptability of Al coverage can be evaluated easily within a short time thereby enabling the judgement confirming the high reliability upon the manufacturing processes to be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a technology for evaluating the quality and reliability of semiconductor circuit wiring at the manufacturing stage.

[Conventional technology]

For technology related to failure analysis inside semiconductor chips in semiconductor integrated circuit (IC) packaging methods, see Nikkei Microdevices J I47, p109-pi 10, published by Nikkei McGraw-Hill on January 1, 1986, on logic circuits. A laser prober technique has been described that analyzes internal logical state deafness by detecting the photocurrent generated when a laser beam is irradiated to a PN junction. According to the above technology, when a laser prober is used to move an object to be inspected between predetermined irradiation areas, the laser output is reduced or cut off, and the laser is positioned in the scanning path of the beam. This prevents circuits from malfunctioning due to laser irradiation and improves the accuracy of logic analysis.

Implementing this laser blower technology requires expensive equipment and is not necessarily common. Furthermore, it is difficult to detect in advance future failures.

For A-type (aluminum) wiring in semiconductor circuits, in many cases the 'fir' wires of AA wiring at the base step are used.
Coverage evaluation regarding thinning of the P film has become a problem.

Conventional A4? As a wiring coverage evaluation method, scanning electron microscopy (SEM) is used.
Sample cross-sections are observed using a tron microscope (Tron Microscope) K, and life tests are conducted to examine deterioration due to long-term energization and thermal stress.

[Problem to be solved by the invention]

However, the observation using the SEM described above has problems in that it takes time to prepare the sample and, moreover, it takes a long time to perform the life test, and neither of these methods is suitable as an evaluation method within the manufacturing process. In addition, both tests are destructive tests.

The present invention aims to solve the above-described drawbacks of the prior art and to provide a semiconductor device manufacturing technique that can be evaluated in a short time.

[Means to solve the problem]

In order to achieve the above object, in the method for manufacturing a semiconductor device of the present invention, a test dummy wiring circuit (TEG) is formed on a part of the wafer at the semiconductor wafer stage, and the dummy wiring is blown. A current is applied using μ, and the wiring in the semiconductor circuit is evaluated based on the value of the fusing current.

[Effect]

According to the method for manufacturing a semiconductor device configured as described above, in a wafer having wiring with poor coverage, fusing i! The current shows a low value, and by managing this current value, A
2. It is possible to easily judge whether the quality of the wiring is good or bad.

Moreover, according to this method, evaluation can be performed at the same time as the probe test and does not require a long period of time unlike a life test.

Furthermore, since a dummy wiring circuit for testing is used, a cross-section taken by SEM! ! There is no need to destroy the conductor wafer or the semiconductor chip during inspection or life test. [Embodiment] An embodiment will be described with reference to the drawings.

+11 Figures 1 and 2 are single-layer people! This is an example of TEG (test dummy wiring circuit) that targets wiring, that is, a contact T of lt wiring is placed on a part of the wafer.
A case in which an EG is provided is shown, with FIG. 1 being a plan view and FIG. 2 being a longitudinal sectional view.

1 is a Si substrate, 2 is an impurity diffusion region such as a paste, 3 is an oxidized FIX (S + 01 film), 4 is a contact hole, and 5 is an A! The wiring has a 5 Tx pattern as shown in FIG. The dimensions (diameter, depth) of the contact hole 4 in this TEG and the dimensions (width, thickness) of the AA wiring are the same as the dimensions of the contact hole in the semiconductor circuit formed on the wafer and the dimensions of the A1 wiring.

A, 6 After the wiring is formed, as shown in Fig. 2, a blow μ (indicated by arrows A and B) is brought into contact with both terminals 5a and 5b of the wiring, and a current is applied to the contact hole TEG. Measure the fusing current.

If the fusing current is significantly lower than the value determined by the A, 6 wiring width and thickness, people! You can see that the fuse is blown in areas with poor coverage.

(2) FIGS. 3 to 4 are examples of a TEG that targets two layers of A2 wiring, that is, a TEG is installed on the first layer of A2 wiring 6 through a through hole 9 in an interlayer insulating film 7. Connect the 2nd wiring #8'Y to the 2nd layer and connect the A wiring through hole #T
3 is a plan view and FIG. 4 is a longitudinal sectional view.

6 is the first layer A! Wiring, 7 is interlayer insulating film, 8 is '2nd H
IAA wiring, 9 is a through hole.

After forming the A2 wiring, blow μ (arrow A
, C) in contact with both wires (8a + 6c) to cause melting in the through-hole TEG 1! Measure the flow.

Also, blow μ to both terminals 8a and 6c of A1 wiring of TEG.
By bringing them into contact with each other, it is possible to inspect whether the conduction state between the first layer A1 wiring 8 and the second layer A4 wiring 6 is good or bad.

(3: Figure 5 shows the protrusion (step) 10 on the wafer.
This shows the coverage state of the A2 wiring (TEG) caused by the above, where lal indicates good coverage and lbl indicates poor coverage.

FIG. 6 shows the shape of a person caused by the stepped portion 11 of the recess (contact hole, through hole/L/) on the wafer! wiring(
TEG) indicates the coverage state, where lal indicates good coverage and (bl indicates poor coverage).

In either case, the Affl wiring above the stepped portion is targeted, and the TEG pattern can be freely selected.

Note that TEG refers to any location within a chip on a wafer,
It can be provided at any location in the chip boundary area (scribe area).

〔Effect of the invention〕

Since the present invention is constructed as described above, it achieves the following effects.

With the TEG formed on the wafer, A! It is possible to easily evaluate the quality of coverage in a short time, and it is possible to make judgments for the purpose of increasing reliability in the manufacturing process.〇The present invention is applicable to Effects can also be obtained when applied to a multilayer wiring board having a multilayer wiring board.

[Brief explanation of the drawing]

1 and 2 show examples of TEG for one-layer AA wiring, in which FIG. 1 is a plan view and FIG. 2 is an A of FIG.
-A sectional view. Figures 3 and 4 are people in the second layer! TEG for wiring
FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line AA in FIG. 3. Fig. 5 181, (bl is a cross-sectional view showing the state of A2 wiring coverage in the convex part, lal shows the case of good coverage, and fbl shows the case of poor coverage. 6 is a cross-sectional view showing the wiring coverage state, where lal indicates good coverage (bl indicates poor coverage) 1...Si substrate, 2...diffusion region, 3...oxide film, 4... Contact hole, 5... people! Wiring, 6...
...First layer A4 wiring, 7...Interlayer insulating film, 8...Second notification A1 wiring, 9...Through hole, 10...A,
! 3 wiring, 11...insulating film. Figure 1 Figure 3 Diagram 2 Figure 4

Claims (1)

[Claims] 1. A semiconductor circuit corresponding to a plurality of semiconductor chips is formed on one main surface of a semiconductor wafer, and a dummy wiring circuit for testing is formed on a part of the surface of the wafer, and a test dummy wiring circuit is formed on a part of the wafer surface. A method for manufacturing a semiconductor device, comprising applying a current using a prober and evaluating the quality and reliability of wiring in the semiconductor circuit based on the value of the fusing current. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the test dummy wiring has a step formed by an insulating film and a metal film, and a metal film wiring is formed thereon.