JPH04137177A - Logic circuit composition system - Google Patents

Abstract

PURPOSE:To automatically generate an inter-block network list by calculating the fan-in value of the input signal of each logic circuit block and the fan-out value of the output signal and composing connections between blocks according to the calculation results. CONSTITUTION:The network list 11 of respective blocks is given the signal name, composed of a name, a symbol indicating a polarity, and a number for discrimination from other signals, in the output signal of each block and a signal name, composed of a name showing a function and a symbol indicating a polarity, in the input signal. A calculating means 13 inputs the list 11 and a library 12 containing fan-in values and fan-out values of primitive blocks used in the respective logic circuit blocks, and calculate the fan-in values of input signals of the respective logic circuit blocks and fan-out values of output signals. A composing means 14 composes the connection between the blocks for the respective output signals of the respective blocks according to the calculation results of the means 13 so that fan-out limitations are satisfied for input signals having the same function name and polarity with the signals, and outputs the inter-block network list 15.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic circuit synthesis method, and more particularly to a method for automatically synthesizing a netlist between blocks from a netlist of a plurality of divided logic circuit blocks. .

[Conventional technology]

Conventionally, when dividing a logic circuit into statistics, as shown in Figure 2, the number of signals between blocks is determined based on the fan-out value on the output side, the fan-in value on the input side, and the polarity. It was necessary to define a suitable name (A+00°A-00, A-Of).

[Problem to be solved by the invention]

In the conventional partitioning statistical method described above, it is necessary to assign a unique name to the input/output signal of each block, which is predetermined at the time of designing each block. The disadvantage is that it is easy to make mistakes when making connections.

[Means to solve the problem]

In the logic circuit synthesis method of the present invention, during division statistics, the output signal is given a signal name consisting of a name indicating its function, a symbol that can distinguish its polarity, and a number to distinguish it from other signals with the same function name. A netlist of multiple logic circuit blocks designed by giving input signals a signal name consisting of a name indicating its function and a symbol that can determine polarity;
A library storing fan-in values and fan-out values of primitive blocks used in each logic circuit block, and a netlist and library of the plurality of logic circuit blocks are input, and an input signal of each logic circuit block is generated. A means for calculating a fan-in value and a fan-out value of an output signal, and based on the calculation results, a fan-out limit is set for each output signal of each block for an input signal having the same function name and polarity as that signal. and means for composing connections between blocks so as to satisfy the requirements.

Furthermore, the logic circuit synthesis method of the present invention gives the output signal a signal name consisting of a name indicating its function and a symbol that can distinguish its polarity during division statistics, and gives the input signal a name indicating its function and polarity. A netlist of multiple logic circuit blocks designed by giving signal names composed of distinguishable symbols and fan-in and fan-out values of primitive blocks used in each logic circuit block is stored. means for calculating fan-in values of input signals and fan-out values of output signals of each logic circuit block using a library, a netlist of the plurality of logic circuit blocks, and the library as input; Immediately following the output signal by detecting polarity mismatches and fanout errors that may occur when connecting the function name signals, and generating as many buffers or inverters as necessary to correct the errors, if any. A means to add a new function name, polarity, and number to the output signal of a buffer or inverter, and for each output signal of each plotter, synthesize connections between blocks for input signals with the same function name and polarity as that signal. and the means to do so.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, one embodiment of the present invention is a logic circuit synthesis method that automatically synthesizes a netlist 15 between blocks from a netlist 11 of a plurality of logical blocks that have been divided and designed. During split design, the output signal is given a signal name consisting of a name indicating its function, a symbol to distinguish its polarity, and a number to distinguish it from other signals with the same function name, and the input signal is given its function. The library 12 is a file that stores the fan-in values and fan-out values of primitive blocks used in each logic circuit block. . The calculation means 13 includes a netlist 11 of a plurality of logic circuit blocks and a library 1.
2 and calculates the fan-in value of the input signal and the fan-out value of the output signal of each logic circuit block, and the connection synthesis means 14 calculates the fan-in value of the input signal and the fan-out value of the output signal of each logic circuit block, based on the calculation results, for each output signal of each block. This is a means of synthesizing connections between blocks to satisfy fan-out restrictions for input signals with the same function name and polarity.

FIG. 2 shows a block diagram of a logic circuit in one embodiment of the present invention. In FIG. 2, net IJ lists between a plurality of logical circuits that have been divided into sections are stored. File 1
1, each block's output signal is given a signal name consisting of a name indicating its function, + and - symbols indicating polarity, and a number to distinguish it from other signals with the same function name, An input signal is given a signal name consisting of a name indicating its function and + and - symbols indicating polarity.

The calculating means 13 receives as input a netlist 11 of each block and a library 12 storing fan-in values and fan-out values of primitive blocks used in each logic circuit block, and calculates the fan of the input signal of each logic circuit block. Calculate the in value and fan-out value of the output signal. The synthesizing means 14 synthesizes the connections between the blocks based on the calculation result of the calculating means 13 so that the fan-out restriction is satisfied for the input signal having the same function name and polarity as each output signal of each block. For example, connections between blocks as shown in FIG. 5 are synthesized from the blocks shown in FIG. 2, which are output as the inter-block netlist 15.

Next, FIG. 3 shows another embodiment of the present invention. In FIG. 3, another embodiment of the present invention is a logic circuit synthesis method that automatically synthesizes a netlist 26 between blocks from a netlist 21 of a plurality of dividedly designed logic circuit blocks. List 21 shows that during split design, an output signal is given a signal name consisting of a name indicating its function and a symbol that can distinguish its polarity, and an input signal is given a signal name consisting of a name indicating its function and a symbol that can distinguish its polarity. The library 22 is a file storing fan-in values and fan-out values of primitive blocks used in each logic circuit block. Calculation means 23 receives the netlist 21 of a plurality of logic circuit blocks and library 22 as input, calculates the fan-in value of the input signal and the fan-out value of the output signal of each logic circuit block, and performs fan-out error detection and buffering. The generating means 24 detects polarity mismatches and fan-out errors that may occur when connecting signals with the same function name based on the results of the calculating means 23, and detects the polarity mismatch and fan-out error that may occur when connecting signals with the same function name. It has a means for generating a buffer or an inverter and adding it immediately after the output signal to give a new function name, polarity, and number to the output signal of the buffer or inverter, and an inter-block connection and synthesis means 26 for each output of each block. This is a means of synthesizing connections between blocks for input signals that have the same function name and polarity as the signal.

FIG. 4 shows a block diagram of a logic circuit in one embodiment of the present invention. In FIG. 4, a file 21 in which a netlist between a plurality of dividedly designed logic circuits is stored includes a name indicating its function, + and - symbols indicating polarity, and other symbols for the output signal of each block. A signal name consisting of a number to distinguish it from signals with the same function name is given, and an input signal is given a signal name consisting of a name indicating its function and + and - symbols indicating polarity. ing. File 12
is provided with a library that stores fan-in and fan-out values for primitive blocks used within each logic circuit block.

The calculation means 23 calculates the fan-in value of the input signal and the fan-out value of the output value of each logic circuit block using the netlist 11 and library 12 of each block as input, and the generation means 24 calculates the fan-in value of the input signal and the fan-out value of the output value of each logic circuit block. It detects polarity mismatches and fan-out errors that may occur when connecting signals with the same function name, and if there are errors, generates and outputs as many buffers or inverters as necessary to eliminate the errors. Add immediately after the signal,
Give a new function name, polarity, and number to the output signal of the buffer Φ inverter. Furthermore, the connection synthesis means 15 synthesizes connections between blocks for input signals having the same function name and polarity as each output signal of each block, and outputs the result as an inter-block netlist 16. For example, from blocks as shown in FIG. 4, connections between blocks as shown in FIG. 5 are synthesized.

〔Effect of the invention〕

As described above, the present invention has the advantage that when performing divided design of a logic circuit, the method of assigning input signal names to each logic circuit block is simplified, and a netlist between blocks can be automatically generated.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram for explaining one embodiment of the present invention, Fig. 3 is a diagram showing another embodiment of the invention, Fig. 4 5 is a circuit diagram for explaining another embodiment of the present invention, and FIG. 5 is a circuit diagram for explaining a conventional technique. 11.21... Netlist of each block, 12゜2
2... Library, 13.23... Fan-out of each block, fan-in value calculation means, 14.24...
Inter-block connection synthesis means, 15. 26... Inter-block netlist, 24... Fan-out error detection and buffer generation means.

Claims (1)

[Claims] 1. In a method for automatically synthesizing a netlist between blocks from netlists of a plurality of logic circuit blocks subjected to division statistics, an output signal has a name indicating its function and polarity is determined during division statistics. give a signal name consisting of a symbol that can be used and a number to distinguish it from other signals with the same function name,
A netlist of multiple logic circuit blocks designed by giving input signals a signal name consisting of a signal indicating its function and a number to distinguish it, and primitive blocks used within each logic circuit block. Calculate the fan-in value of the input signal and the fan-out value of the output signal of each logic circuit block by using as input a library storing fan-in values and fan-out values, and the netlist and library of the plurality of logic circuit blocks. and means for synthesizing connections between blocks so that each output signal of each block satisfies a fan-out restriction for an input signal having the same function name and polarity as that signal, based on the calculation result thereof. A logic circuit synthesis method featuring the following. 2. In the logic circuit synthesis method according to claim 1, based on the calculation results of the means for calculating the fan-in value of the input signal and the fan-out value of the output signal of each logic circuit block,
Detects polarity mismatches and fanout errors that can occur when connecting signals with the same function name, and generates as many buffers or inverters as necessary to correct the errors, if any, on the output signal. A logic circuit synthesis method characterized by comprising means for adding a function name, polarity, and number to an output signal of a buffer or an inverter immediately after the buffer or inverter.