JPH0612557B2 - Logic device delay check method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to computer aided design of theoretical devices, and more particularly to computerized check of flip-flop to signal delays in large scale logic devices.

[Conventional technology]

In the design process of the logic device, the delay check is indispensable for verifying the validity of the logic setting and the placement / wiring design, and for calculating the signal delay (that is, signal propagation time) of each signal path from the design information. , A computer is used.

In the conventional method of day delay check by computer, as described in "Signal delay check system" (Ryotaro Kamikawai et al.), Which is contained in the collection of papers of the National Conference of IEICE Information and Systems Division, 1979, For the flip-flop (or latch) pair of, the delays of the signal paths between the flip-flops are calculated, and the maximum delay path and the minimum delay path are determined and output.
The output typically takes the form of a printout of the listing and storage on a file storage device such as a disk. The designer reads the list or the displayed file data and decides where the design change is necessary. The data accumulated in the file storage device is also used to create various statistical data.

[Problems to be Solved by the Invention]

In the case of a large-scale logic device, a huge number of flip-flops are included, so that the computer time and output data amount required for delay calculation are enormous. With regard to the amount of output data, in the case of a complicated circuit such as a high-speed multiplier / divider, it is not uncommon for the conventional method list to reach several thousand pages per package.

The computer time problem could be solved relatively easily by the introduction of high speed machines such as supercomputers. However, solving the output data volume problem is not easy. The design support computer system has various tasks (eg, logic simulation, automatic place and route processing, etc.) that must be performed in addition to the delay calculation, and they also require a large disk capacity. Therefore, it is difficult to save huge disk capacity for delay calculation. Also, it is extremely difficult to read and correct a delay defect by reading a huge amount of lists or display data, and it becomes practically impossible when the list per package is in the order of 1,000 pages.

An object of the present invention is to reduce the output data amount of the delay calculation, thereby reducing the required disk capacity and facilitating the designer's investigation and correction of the delay defect.

[Means for Solving the Problems]

According to the present invention, the daily check is performed in two stages, a functional level check and a detailed level check.
In the functional level check, the flip flops are grouped into functional groups (typically registers) and the computer determines the worst signal delay (usually the maximum and minimum delay) between each pair of functional groups. ,Output. In the next detail level check, the computer checks the signal delay between the individual flip flops and outputs the result, for only the functional group pairs specified by the user.

As a modification, in the function level check, it is determined whether or not the worst signal daily between each pair of function groups is within a predetermined allowable range, and only the worst signal delay not within the allowable range is output. May be.

[Action]

The output data resulting from the function level check is one set for each functional group pair and is not affected by the number of flip flops contained in them, and therefore its amount is significantly smaller than the output data of the conventional method. This reduction rate is even greater in the variant that outputs only those that are not within the allowable range. The designer uses this output data to investigate the delay failure, corrects the logic design as necessary, and if there is a delay failure function group pair that cannot be dealt with by the modification of the logic design, specifies the function group pair. Then, let the detail level check be performed. This detail level check is performed only for a relatively small number of functional group bodies, and can be performed separately for each functional group pair, so that the required disk capacity and verification effort are negligible. . The output data of the detail level check is used to correct the layout design.

〔Example〕

FIG. 1 is a flow chart showing the entire delay defect correction process performed by using one embodiment of the present invention. After the initial logic design and layout and wiring design 1 are completed, first, the function level delay calculation 2 is performed. In the function level delay calculation 2, all flip flops (hereinafter abbreviated as FF) are grouped into registers and other function groups,
The maximum and minimum delays between these functional groups are determined and output as a functional level delay list 5 and a functional level delay file 6. The delay calculation is performed for all FF paths, but the result may be discarded except for the maximum and minimum delays between functional groups.

One of the methods for allowing the computer to identify the functional group to which each FF belongs is to manually specify each functional group and the FF or FF signal belonging to it. For example, as shown in FIG.
Serial numbers are attached to 2, 23, ..., And information indicating the correspondence between each group number and the FF signal name output from the group is given as a functional group designation file 24 as shown in FIG. 2 (b).

Another method is to embed the functional group identification information in the design information itself, which includes the F
It is necessary to predefine rules for instructions such as F and FF signals. For example, the FF shown in FIG.
In the signal names AB (1), AB (2), etc., the English character before the parentheses indicates the functional group, and the number in the parentheses indicates the serial number of the FF in the functional group. According to this nomenclature, the functional level delay calculation program 26 can know the functional group that is the generation source of each FF signal directly from the design information 25.

The function level delay calculation program 26 uses the group identification information as described above to generate the table A shown in FIG.
And B. Table B is a list of all FF signal names, and table A shows the number of FF signals generated from each functional group and the start address of those FF signals in table B. Then, the functional level delay signal program 26 sequentially reads the design information regarding the successive FF signals of the successive functional groups with reference to the tables A and B, calculates the delay time, and creates the table C. Table C shows start point function group 31
For each pair of the end point function group 32, the maximum value 35 and the minimum value 38 of the delay values, and the start points FF33 and 36 and the end points FF34 and 37 of the paths having these delay values are included.

An example of the processing means for creating the table C is shown in the form of a flow chart in FIG. In the initial value setting 40, a sufficiently small value is set in the maximum delay value column of the table C, and a sufficiently large value is set in the minimum delay value column. After setting the initial value, the function level delay calculation program selects one start point FF and one end point FF by referring to the tables A and B (41, 42), and determines the delay value between them as the design information. Calculate using (4
3). The obtained delay value is first compared with the maximum delay value 35 in the table C (44), and if the former is larger than the latter, the maximum delay value 35 in the table C and the corresponding start point FF number 33 and end point FF. The number 34 is
Replaced by the newly obtained corresponding data (4
5). Subsequently, the newly obtained delay value is compared with the minimum delay value 38 in table C (4
6). This comparison 46 is also performed if the comparison 44 finds that the newly obtained delay value is not greater than the existing maximum delay value. As a result of the comparison 46, if the newly obtained delay value is smaller than the minimum delay value in the table C, the latter and the corresponding starting point F
The F number 36 and the end point FF number 37 are replaced by the newly obtained corresponding data (47). Same starting point FF
Similar processing is repeated for the other starting point FF connected to (48, 42), and the same processing is repeated for the next starting point FF. (49,41). The contents of the finally obtained table C are output as a function level delay list 5 and a function level delay file 6.

Returning to FIG. 1, using the functional level daily list 5,
Functional level delay verification 3 is performed. If neither the maximum delay value nor the minimum delay value exceeds a permissible limit value for a certain function group pair, it is determined that there is no delay defect in any path between the FFs belonging to these function groups. Good. If at least one of the maximum delay value and the minimum delay value exceeds the allowable limit value, the function level delay defect countermeasure 4 is taken. This measure is to increase / decrease the number of gate stages, change the type of gate, and change other logics. This type change can be made uniformly for all paths or only for individual paths. Therefore, we do not need a list of all FF pair delay data. The modified design is again inspected in the same way. Many of the remarkable delay defects found at the functional level delay verification stage are cured by the above measures.

When it is determined that it is difficult to cure by the above measures, the detail level delay calculation 7 is performed on the function group pair in question. The functional group pairs to check are, for example,
As shown in FIGS. 5 (a) and 5 (b), a pair of functional group identification codes (English characters before parentheses) in each FF signal can be designated by giving them as a functional group pair designation file 51.

The detail level delay calculation program 52 determines the maximum delay and the minimum delay for all FF pairs belonging to the specified functional group pair by a method similar to the conventional method,
The detail level day list 10 and the detail level day file 11 are output. Since many delay defects are already removed by the function level delay defect countermeasure 4, there are few function group pairs that require detailed level delay calculation, and this delay calculation should be performed separately for each function group pair. You can Therefore,
Both the volume of the list and the required disk capacity are low enough.

The detail level delay verification 8 is performed using the detail level delay list 10, and the detail level delay defect countermeasure 9 is taken. This measure is to change the gate position, pin position, wiring pattern, and other layout / wiring. In general, the density of various components and wiring patterns in the package is extremely high, and there are few vacant spaces for changes, so it is impossible to change the placement and wiring in one path without changing in some other paths. . Therefore, it is necessary to know how much room there is in Pal's delay near the pulse in question. For this reason, output of the delay data of all FF pairs belonging to the same functional group pair is required. The modified design is again inspected in the same way, and finally the delay failure is eliminated.

FIG. 6 shows the effect of the present invention in the case of a 64-bit binary full adder. The output lines of the register A61 and the register B62 are connected to the register C64 through the binary full addition logic circuit 63 including carry logic. When the pair of FFs connected by at least one path is counted as 1FF section, the connection from register A to register C consists of 2080FF section, and the connection from register B to register C also consists of 2080FF section. Therefore, according to the conventional method, 4160FF
The maximum and minimum delays are output for each of the sections. On the other hand, the functional level delay list of the present invention is the maximum and minimum delays from register A to register C, and register B to register C.
Up to the maximum delay and the minimum delay, and the amount of data is almost equal to that in the 2FF section. Therefore, the amount of output data is reduced to 0.1% or less. The reduction rate depends on the complexity of the circuit, but is 1/100 on average
A reduction rate close to that can be expected.

As part of the functional level delay calculation (Fig. 4), the maximum and minimum delay values of each functional group pair are compared with their respective predetermined allowable limit values, and the presence or absence of a delay defect is determined by this. Then, it may be changed so that only the delay data of the functional group pair determined to have the delay defect is output. As a result, the amount of output data is further greatly reduced, and manual function level delay verification can be made almost unnecessary.

For detail level delay data, since there are only a few feature group pairs that are subject to the detail level check, instead of outputting only the maximum and minimum delays, all signal paths between each specified pair of feature groups are You may output the delay data.

Also, the delay check according to the present invention may be performed at an intermediate stage of design.

〔The invention's effect〕

According to the present invention, both the file storage capacity required for the delay calculation and the amount of data that a person has to look up are significantly reduced as compared to the conventional method, resulting in a large scale logical device. Also, the inspection of the day defect becomes extremely easy.

[Brief description of drawings]

FIG. 1 is a flow chart of a delay defect correction work using an embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of a function group designation method, and FIG. 3 is a process of function level delay calculation. 4 is a schematic diagram of information used in FIG. 4, FIG. 4 is a flow chart of an example of a main part of a function level delay calculation, FIG. 5 is a schematic diagram showing an example of a function group pair designation method, and FIG. The figure shows the effect of the present invention for a binary full adder. 2 ... 1st check step functional level delay calculation, 6 ... functional level delay list, 7 ... functional level delay file, 8 ... 2nd check step detailed level delay calculation, 12 ... detailed level delay List, 13 ... Detail Level Day File.

Claims (2)

[Claims] 1. A first check for determining and outputting a worst signal delay between functional groups of the flip-flops in the process of checking the inter-flip-flop signal delay of a logic device including a large number of flip-flops by a computer based on design information. A delay check method having a step and a second check step for checking the signal delay between individual flip flops for a specified functional group pair and outputting the result. 2. The method of claim 1, wherein the first check step includes a step of determining whether the worst signal delay between each pair of functional groups is within a predetermined tolerance range. A delay check method that outputs only the worst signal delay that is not within the range.