JP2734966B2 - Delay optimization system for sequential circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay optimization of a sequential circuit of a semiconductor integrated circuit having a property that a delay value of a critical path of a sequential circuit composed of a combinational circuit and a flip-flop is correlated with the number of inputs of the combinational circuit. The present invention relates to a method and, more particularly, to a delay optimization system for a sequential circuit for realizing delay averaging of a critical path.

[0002]

2. Description of the Related Art A conventional method of optimizing delay of a sequential circuit is as follows.
As shown in FIG. 9, a circuit dividing unit 11 that divides a circuit by flip-flops controlled by the same clock, a logic extracting unit 12 that receives an output of the circuit dividing unit 11 as an input and extracts combinational logic, and an element delay table 15 A delay calculating unit 13 for calculating a delay of a combinational logic part from the input unit; a scheduling unit 14 which receives an output of the delay calculating unit 13 as input and performs scheduling so that delay values are equally distributed among the flip-flops; 14
Has a circuit changing unit 16 that changes the circuit according to the scheduling result. In the conventional delay optimization of a sequential circuit, generally, a method that has good quality but requires a long processing time, such as extracting all the combinational circuits and reinserting flip-flops, is generally used.

[0003] Conventionally, as a delay analysis method for performing delay analysis between LSIs mounted on a printed circuit board, for example, as described in Japanese Patent Application Laid-Open No. 4-114280, a plurality of LSIs are mounted. The circuit data of the printed circuit board is read, and all the paths from the flip-flop to the LSI input / output terminal are searched in each LSI on the read circuit data, and both ends of the searched paths are the same and the signal delay is the maximum. Identify the critical path that is to be used, specify the flip-flop pair connected by the critical path sharing one end of the path, and specify the target path from one of the specified flip-flop pair to the other via the critical path between the two. There is one that performs delay analysis.

[0004]

SUMMARY OF THE INVENTION Delay of conventional sequential circuit
Optimization optimizes the entire sequential circuit controlled by the same clock.
Obtain the logical expression, calculate the delay value, and calculate the delay value.
Each flip so that the
Combination circuits were distributed between flip-flops.
It takes time to calculate the whole logic and delay.
There was a problem.

The present invention has been made to solve such a problem.
Reduced delays in critical areas,
Fast averaging of delays between lip flops
The purpose is to obtain a delay optimization system for sequential circuits.
You.

[0006]

SUMMARY OF THE INVENTION A delay of a sequential circuit according to the present invention.
Optimization system consists of combinational circuits and flip-flops
The delay value of the critical path of the sequential circuit consisting of
Semiconductor with the property of being correlated with the number of input circuits
Flip-flops in sequential circuits
Division means for dividing into groups controlled by the same clock
And each group divided by this dividing means
Connect the flip-flop to the node and flip-flop
The number of branches input to each node of the graph
Graph creator that creates a directed graph as an attribute of the
And the directed graph obtained by the directed graph creation means.
The first node exceeding the permissible delay value on the rough is the processing target
Then, the L second nodes located on the input side are integrated into one.
A node integrating means for creating a combined third node;
A first node for changing a delay value between a first node and a third node;
And the first node is a processing target.
And generating a fourth node obtained by dividing it into I nodes
Dividing means, located at the first node and its output side
Second delay replacement for changing the delay value of the fifth node
Means and directed where node integration and delay replacement have been performed
Flip-flop integration and combination according to graph
First circuit changing means for moving the shift circuit;
According to a directed graph with
To divide the flip-flop and move the combinational circuit.
A second circuit changing means, and the node integrating means.
And first delay changing means and the node dividing means
Change the target of the second delay replacement means
Average the complexity of combinational circuits by repeating
It is something to do.

[0007] In addition, a forward path circuit according to another invention of the present invention.
The delay optimization system is a semiconductor integrated circuit according to the first invention.
In a circuit, flip-flops in a sequential circuit
Division means for dividing into groups controlled by locks,
Flip by each group divided by the dividing means
Graph connections between flops and nodes and flip-flops
And the number of branches input to each node as a delay value, this delay value
Directed graph creation to create a directed graph as an attribute of a node
Generating means and the directional graph
Process the first node exceeding the allowable delay value on the directed graph
Elephant and a first branch having the first node as an output node
L (L is an integer of 2 or more) is selected and placed on the input side of the first branch.
A third node in which L second nodes to be placed are integrated into one
Node integration means for creating a node, delay of the first node
L-1 is subtracted from the delay value of the third node,
Delay changing means for changing the sum of delay values of delay
And the first node is a processing target and the first node is I
Generate the fourth node divided into I (I is an integer of 2 or more)
And a delay value of the first node
Divided into four and attached to the fourth node on the output side of the first node
A second adding I-1 to the delay value of the located fifth node;
Delay replacement means, and the above-mentioned node integration and delay replacement
The free path in the circuit to be processed is
Integration of flip-flops and flip-flop output side
Separate combination circuit and move to input side of flip-flop
First circuit changing means to be operated, and the above-described node division and delay
The number of times to process according to the redirected directed graph
A flip-flop that splits a flip-flop on the road
Split the combinational circuit on the input side of the flip-flop and
A second circuit changing means for moving to the output side;
Code integration means and first delay replacement means, and
Divide means and second delay changing means
By changing the target and repeating, the combination circuit
Averaging the number of inputs and flattening the delay time between flip-flops
It is intended to be equalized.

[0008]

According to the present invention, the number of inputs of the combinational circuit is reduced, and the combinational circuit of that portion moves between the other flip-flops. Further, the processing range for eliminating the critical path is limited.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a delay optimization system for a sequential circuit according to the present invention. In FIG. 1, reference numeral 1 denotes a circuit dividing unit, which constitutes dividing means for dividing flip-flops in a sequential circuit into groups controlled by the same clock. Reference numeral 2 denotes a directed graph creating unit which receives the output of the circuit dividing unit 1 as an input. In each group, a flip-flop is a node, a connection between the flip-flops is a branch of the graph, and the number of input branches to each node is a node representing a delay value. And constitutes a directed graph creating means for creating a directed graph having the attribute of. Reference numeral 3 denotes a node integration unit of a directed graph which receives the output of the directed graph creation unit 2 as an input, and processes the first node exceeding the allowable delay value on the directed graph and locates L (L: an integer equal to or greater than 2) located on the input side thereof. ) Number of second nodes are integrated into one to form a third node.

Reference numeral 4 denotes a first delay changing unit which receives an output of the node integration unit 3 of the directed graph as an input, and sends an output to the node integration unit 3 of the directed graph. This constitutes a first delay changing means for changing a value. Reference numeral 5 denotes a node division unit of a directed graph which receives the output of the first delay changing unit 4 as an input, and processes the first node into a fourth node.
And a node dividing unit for generating the node. 6
Takes the output of the node division unit 5 of this directed graph as input,
A second method for sending the output to the node division unit 5 of the directed graph
Of the first node and a fifth node located on the output side of the first node constitute second delay changing means.

Reference numeral 7 denotes a first circuit changing unit which receives the output of the circuit dividing unit 1 and the output of the first delay changing unit 4 as inputs, and integrates flip-flops according to a directed graph in which node coupling and delay changing are performed. And the first circuit changing means for moving the combinational circuit. 8 is the first
A second circuit changing unit which receives the output of the circuit changing unit 7 and the output of the second delay changing unit 6 as inputs, splits the flip-flop and combines the flip-flops in accordance with a directed graph in which node splitting and delay changing are performed. This constitutes a second circuit changing means for performing the movement. Then, the complexity of the combinational circuit is averaged by repeating the node integrating means and the first delay changing means and the node dividing means and the second delay changing means while changing the targets of the respective means. .

Then, the directed graph creating unit 2 sets the flip-flop as a node in each group, the connection between the flip-flops as a branch of the graph, a delay value based on the number of branches input to each node, and the delay graph as an attribute of the node. , And the directed graph node connecting unit 3 treats a first node exceeding the allowable delay value on the directed graph as a processing target and sets the first node as an output node to a first L nodes ( L: an integer equal to or greater than 2) to form a third node by integrating L second nodes located on the input side of the first branch into one. The first delay changing unit 4 constitutes a first delay changing unit for subtracting L-1 from the delay value of the first node and replacing the delay value of the third node with the sum of the delay values of the second nodes. , The directed graph node dividing unit 5 constitutes a node dividing means for generating a fourth node obtained by dividing the first node into I (I is an integer of 2 or more) with the first node as a processing target. .

The second delay changing section 6 divides the delay value of the first node into I pieces, attaches it to the fourth node, and adds the I value to the delay value of the fifth node located at the output side of the first node. The first circuit changing unit 7 connects the flip-flops in the circuit to be processed according to the directed graph in which the node integration and the delay replacement are performed, and outputs the flip-flop output side. A first circuit changing means for separating the combinational circuit and moving it to the input side of the flip-flop is constituted. The second circuit changing unit 8 divides the flip-flop in the circuit to be processed according to the directed graph in which the node division and the delay replacement are performed, separates the combinational circuit on the flip-flop input side and moves the combinational circuit to the flip-flop output side. It constitutes a second circuit changing means. Then, by repeating the objects of the node integrating means and the first delay changing means and the node dividing means and the second delay changing means, the number of inputs of the combinational circuit is averaged, and the delay time between flip-flops is averaged. It is configured to be.

FIG. 2 is a flowchart for explaining the operation of FIG. 1. FIG. 2A is a flowchart of the directed graph node integration unit 3 and the first delay replacement unit 4 of FIG. 1, and FIG. 2B is a flowchart of the directed graph of FIG. Node division unit 4
3 shows a flowchart of the second delay changing unit 6. Steps 101 to 113 and step 201 in FIG.
At steps 211 to 211, a predetermined process is executed. FIG. 3 shows an example of a circuit to be processed in the present invention.
... K indicates a flip-flop. FIG. 4 is an explanatory diagram showing an example of a directed graph created from FIG.
(B)... (K) indicate nodes, and (1), (2).
.. (5) indicates the attribute of the node. FIG. 5 is an explanatory diagram showing an example of a directed graph obtained by modifying FIG. 4, FIG. 6 is an explanatory diagram showing a change in a circuit accompanying the transformation of the directed graph from FIG. 4 to FIG. 5, and FIG. 7 shows a directed graph obtained by modifying FIG. FIG. 8 is an explanatory diagram showing a change in the circuit accompanying the transformation of the directed graph from FIG. 5 to FIG.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. Here, FIGS. 1 and 2
How the circuit of FIG. 3 and the directed graph of FIG. 4 are processed according to the processing flows of (a) and (b) will be described. First, the circuit dividing unit 1 divides a sequential circuit to be processed by a flip-flop controlled by the same clock. Next, the directed graph creation unit 2
, A directed graph is created in which flip-flops of each group are nodes and the connection between the flip-flops is a branch of the graph. Here, the number of branches entering each node represents the number of input signals of the combinational circuit constituting the flip-flop input, and in order to easily represent the delay value reaching that node, the attribute of the node representing the delay value and I do. Here, when the circuit to be processed is FIG. 3, a directed graph as shown in FIG. 4 is created. Here, A and B in FIG.
.. K indicate flip-flops, and FIG.
(B)... (K) are nodes, (1), (2).
Indicates the attribute of the node.

Since the number of input signals to the combinational circuit has a correlation with the complexity of the circuit, the critical path often concentrates on nodes having a large number of input signals.
For this reason, the following processing is performed in order to make the delay value of the node of the created directed graph equal to or less than the specified allowable value. First, the node integration unit 3 of the directed graph selects a first node L having a delay value M exceeding a permissible value N as a processing target from the directed graph, and selecting the first branch L having the first node as an output node. , L located on the input side of the first branch
A third node is created by integrating the second nodes into one. In the first delay changing unit 4, the first
, The delay value of the third node is replaced by the sum of the delay values of the second node. Here, in order to make the delay value equal to or less than the allowable value, the number L of branches to be selected must be M−N + 1. When the nodes are integrated by this process, the delay value of the first node becomes N. However, the new delay value of the integrated third node is
Since the delay value of the second node before integration is added and added, a node having the smallest delay value of the node to be integrated is selected. Accordingly, when the third node exceeds the delay allowable value N, the above processing is performed by replacing the third node with the first node as a new processing target, and inputting the node until the delay allowable value is satisfied. Repeat the process going back to the side.

Then, going back to the entrance of the directed graph,
If the delay cannot be eliminated, the process returns to the initial process, and the number L of branches to be selected is reduced so that the delay value of the integrated third node does not exceed the allowable value. To perform the same processing. For example, in the directed graph of FIG. 4, the allowable value is set to “3”, and the node G having the delay value “5” exceeding the allowable value is set as the processing target. The number of branches selected here is "3", but the sum of the delay values of the nodes F, I, and K to be integrated is "4". The number of selected branches is reduced to “2”. Nodes F and I are F
And the node I is deleted. Although the delay value of the node G is “4” and the allowable value cannot be canceled, the delay value of the integrated node F does not exceed the allowable value. Thereby, the directed graph of FIG. 4 is transformed as shown in FIG.

In the first circuit conversion unit 7, when the node integration and the replacement of the delay value are performed on the directed graph by the above-described processing, the circuit to be processed is changed following the process of the directed graph. By modifying the directed graph from FIG. 4 to FIG. 5, the processing circuit of FIG. 3 is modified as shown in FIG. From the combinational circuit reaching the flip-flop G, the combinational circuit portion of F and I is separated and moved to the input side of the flip-flops F and I. This allows
Since the flip-flops F and I are integrated, the flip-flop I is deleted. Here, in the case of a one-phase synchronous circuit,
Even with this change, the final logic / timing is guaranteed.

The node division unit 5 of the directed graph terminates the processing here if the allowable delay value is satisfied by the above-described node integration. If the delay is not satisfied, the first node is processed. And the first node is I
Generate a fourth node divided into individual nodes. In the second delay changing unit 6, the second branch entering the fourth node is
The first node is divided and assigned to the fourth node, and the number of branches is added to the fourth node as a delay value, and I-1 is added to the delay value of the fifth node located on the output side of the first node. Here, as the number of divisions I, a minimum integer whose delay value after division does not exceed an allowable value is selected.

Here, the original delay value of the fifth node is J, and the divided delay value of the fifth node J + (I-1)
Exceeds the allowable value N, the fifth node is replaced with the first node as a new processing target, and the process proceeds to the output side of the node and repeats the processing until the delay allowable value is satisfied. Then, when reaching the exit of the directed graph, the node cannot be divided any further. If the delay allowable value is not satisfied here, the state of the directed graph before the node division is performed is returned, and the processing is terminated. In the example of FIG. 5, the delay value of the first node G is “4”, which can be made equal to or less than the allowable value by dividing into two. Then, the node G is divided to create a fourth node “G”, and a copy “G” D of the branch GD from the node G
Generate The branch to the node G is divided into two equal parts as much as possible, and one branch group (BG, FG) changes the node to “G”. The delay value of the node G, “G” is the number of divided branches, and is replaced with this value.
By this division, the delay value is added to the fifth node D located on the output side of the node G by "1". here,
Since the delay value of the node D becomes “3” and satisfies the allowable value, the processing is stopped here. Thereby, the directed graph of FIG. 5 is transformed as shown in FIG.

Next, in the second circuit changing section 8,
When the node division and the replacement of the delay value are performed on the directed graph by the above processing, the circuit to be processed is changed following the process of the processing on the directed graph. And FIG.
The circuit of FIG. 6 is changed as shown in FIG. 8 by changing the directed graph from FIG. First, a copy “G” of the flip-flop G is created. Next, the combinational circuit leading to the flip-flop G is divided according to the branch division described above, and moved to the output side of the flip-flop G and the output of "G", respectively. In the case of a one-phase synchronous circuit, the final logic / timing is guaranteed even if this change is made.

[0022]

As described above, the present invention reduces the number of inputs of a combinational circuit in order to reduce the critical path of a sequential circuit determined by the complexity of the combinational circuit between flip-flops, Is moved between the other flip-flops, so that the delay in the critical portion can be reduced and the delay between the flip-flops can be averaged quickly. Also, the present invention limits the processing range for eliminating the criticality, so that when the difference between the critical path delay value and the allowable delay value is small, the processing can be performed at high speed. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a delay optimization system for a sequential circuit according to the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG. 1;

FIG. 3 is an explanatory diagram showing an example of a circuit to be processed in the present invention.

FIG. 4 is an explanatory diagram showing an example of a directed graph created from FIG. 3;

FIG. 5 is an explanatory diagram showing a directed graph obtained by modifying FIG. 4;

FIG. 6 is an explanatory diagram showing a change in a circuit accompanying a transformation of the directed graph from FIG. 4 to FIG. 5;

FIG. 7 is an explanatory diagram showing a directed graph obtained by modifying FIG. 5;

FIG. 8 is an explanatory diagram showing a change in a circuit accompanying a transformation of the directed graph from FIG. 5 to FIG. 7;

FIG. 9 is a block diagram illustrating an example of a conventional method of delay optimization of a sequential circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit division part 2 Directed graph preparation part 3 Directed graph node integration part 4 First delay replacement part 5 Directed graph node division part 6 Second delay replacement part 7 First circuit change part 8 Second circuit change part

Claims (2)

(57) [Claims] 1. A combination circuit and a flip-flop
Combination of critical path delay values of sequential circuits
A collection of semiconductors that have the property of being correlated with the number of circuit inputs
In an integrated circuit, flip-flops in a sequential circuit are controlled by the same clock.
Dividing means for dividing into groups to be divided , and flipping in each group divided by the dividing means.
Connect the flip-flop to the node and the connection between the flip-flops
Branch, the number of branches input to each node
A directed graph creation means for creating a directed graph as an attribute, and a directed graph obtained by the directed graph creation means
The first node exceeding the allowable delay value in
L (L: an integer of 2 or more) second nodes located on the input side
Node to create a third node that integrates
Combining means for changing the delay values of the first node and the third node
A first delay changing means, and the first node is processed and divided into I pieces
Node dividing means for generating a fourth node, a fifth node located on the output side of the first node and the first node
Second delay changing means for changing the delay value of
Therefore, integration of flip-flops and combinational circuits
A first circuit changing means for performing the movement, and a directed graph in which the node division and the delay replacement are performed;
Therefore, the division of the flip-flop and the combinational circuit
A second circuit changing means for performing a movement, wherein the node integrating means and the first delay changing means and
The node dividing means and the second delay changing means
Combination times by changing the target of the means and repeating
A delay optimization system for a sequential circuit, wherein a complexity of a road is averaged . 2. A combination circuit and a flip-flop
Combination of critical path delay values of sequential circuits
A collection of semiconductors that have the property of being correlated with the number of circuit inputs
In the integrated circuit, flip-flops in the sequential circuit are controlled by the same clock.
Dividing means for dividing the data into groups to be controlled , and flickering in each group divided by the dividing means.
Connect the flip-flop to the node and the connection between the flip-flops
Branch The number of branches input to each node is used as the delay value
Create a directed graph with delay values as node attributes
Graph creation means, and on the directed graph obtained by the directed graph creation means
And the first node exceeding the allowable delay value
L first branches (L:
L) that are located on the input side of the first branch
Create a third node by integrating the second node of
A third node by subtracting L-1 from the delay value of the first node.
The delay value of the second node to the sum of the delay values of the second node.
1 delay changing means, and I nodes for the first nodes to be processed.
Generate a fourth node divided into (I: an integer of 2 or more)
And a node dividing means for dividing the delay value of the first node into I
Of the fifth node located on the output side of the first node
A second delay changing means for adding I-1 to the delay value; and a directed graph in which the node integration and the delay changing are performed.
Therefore, integration of flip-flops in the circuit to be processed
Separate the combinational circuit on the flip-flop output side
The first circuit change to move to the input side of the flip-flop
And a directed graph in which the node division and the delay replacement are performed.
Therefore, the division of the flip-flop in the circuit to be processed
Separate the combinational circuit on the flip-flop input side
The second circuit change to the flip-flop output side.
And a further unit, said node integration means and the first delay replacement means and before
The node dividing means and the second delay changing means
Combine by changing the target of the means and repeating
Averaging the number of circuit inputs and delaying between flip-flops
A delay optimization system for a sequential circuit, characterized in that intervals are averaged .