JP2560990B2 - Logic circuit minimization device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage logic circuit optimizing device, and more particularly to a logic circuit minimizing device for reducing the circuit scale.

[0002]

2. Description of the Related Art The following is the first prior art of a logic circuit minimization method. For a logical expression that realizes a multi-stage logic circuit, select a factor that can be divided only by yourself, and divide the logical expression by that factor. Further, the same operation is repeated for the logical expression after the division to generate a minimized multi-stage logical circuit. This is described in "Reference: RK. Brayton, C. McMullen,
"The Decomposition and fa
customization of Boolean anexp
"Recessions", in Proc. ISCAS-8
2, 1982 ".

The second conventional technique is as follows. Wiring is added to the multi-stage logic circuit without changing the logic of the circuit output, or two or more gates are connected to one.
Performs circuit conversion to merge into one gate. Next, redundancy is detected in the circuit and redundancy is removed. The circuit is minimized by repeating these circuit conversion and redundancy removal. In this method, the circuit scale is once increased by the circuit conversion for the circuit whose scale is minimized by the redundancy removal, and the circuit having another minimum value is generated by the redundancy removal. By repeating this, a circuit having a scale closer to the minimum value is generated. This is described in “Reference 1: S. Muroga,
Y. Kambayashi, H .; C. Lay, J. et al. N.
Cullyney, “The Transducio
n Method-Design of Logic
Networks Basedon Permissi
ble Functions ”, IEEE tran
s. Comput. C-38, 10, pp. 1404-
1424, Oct. 1989 ", and" Literature 2: L.
Treville, W .; Joyner, L .; Ber
man, "Global Flow Analysis
in Automatic Logic Design
n, "IEEE Trans. on Comput.,
vol. C-25, no. 1, Jan. 1986 ".

[0004]

In the first prior art described above, miniaturization becomes impossible when the logic circuit becomes large in scale.
This is because the number of terms in the logical expression of a large-scale circuit becomes very large, and a huge amount of memory capacity and calculation time are required to express and simplify the logical expression.

A first object of the present invention is to overcome the problems of the above-mentioned first conventional method, and to provide a minimization device which minimizes a large-scale circuit with a small storage capacity and at a high speed. is there.

The first problem of the above-mentioned second conventional technique is as follows. Since wiring addition and gate merging are small-scale conversions, it is difficult to bring the circuit scale close to the minimum value, and it cannot be sufficiently minimized.

A second object of the present invention is to solve the above problems and to provide a minimization device having an excellent minimization ability for performing circuit conversion having a great effect of bringing the circuit scale close to the minimum value.

The second problem of the second conventional technique is as follows. Since the redundancy of the circuit generated by the circuit conversion cannot be specified at the time of conversion, it is necessary to detect the redundancy of the entire circuit before removing the redundancy. Further, the determination as to whether or not the circuit conversion reduces the circuit scale can be performed only after the redundancy is removed.

A second object of the present invention is to solve the above problems and perform circuit conversion capable of specifying the redundancy to be generated, thereby determining the effectiveness of the circuit conversion at an early stage and further omitting redundancy detection. It is an object of the present invention to provide a minimization device having a high minimization efficiency.

[0010]

SUMMARY OF THE INVENTION A logic circuit minimization device of the present invention is a transition showing a relationship between an input device for inputting a multi-stage logic circuit and a value between wirings in the logic circuit input to the input device. A transition implication graph generation device that generates an implication graph, and a transition implication graph transformation device that transforms the transition implication graph generated by the transition implication graph generation device and reduces the scale A partial circuit generation device that generates the maximum number of partial circuits that can be added to the logic circuit input to the input device from the transition implication graph, and a logic that inputs the partial circuit generated by the partial circuit generation device to the input device. A partial circuit adding device to be added to a circuit, and a redundancy removing device to remove redundancy of a circuit generated by adding a partial circuit in the partial circuit adding device. Characterized in that comprising a location.

[0011]

1 is a block diagram showing the configuration of an embodiment of a logic circuit minimization apparatus according to the present invention.

This logic circuit minimization device is provided with an input device 11
And a transition implication graph generation device 12, a transition implication graph transformation device 13, a partial circuit generation device 14, a partial circuit addition device 15, and a redundancy removal device 16.

In the logic circuit minimization apparatus having the above configuration, a multistage logic circuit is input by the input device 11, and a transition implication graph generation device 12 generates a transition implication graph from the logic circuit.

The transition implication graph transformation device 13 transforms the transition implication graph generated by the transition implication graph generation device 12 to reduce its scale. As a result, the scale of the additional partial circuit generated by the partial circuit generating device 14, which is the subsequent device, can be reduced.

The partial circuit generation device 14 generates all the partial circuits that can be added to the logic circuit input by the input device 11 from the transition implication graph transformed by the transition implication graph transformation device 13. In this partial circuit addition, a plurality of wirings and gates can be added at the same time, so that the applicable range of circuit conversion is larger than that of wiring addition and gate merging. further,
With the transition implication graph transformation device 13, which is the previous device,
Since the transition implication graph is modified, the minimum additional subcircuit is obtained. Moreover, the application range of the circuit conversion is the same as that when the transition implication graph is not transformed. Therefore, since the applicable range of the circuit conversion can be widened and the added partial circuit can be minimized, the circuit conversion is highly effective in approaching the minimum value. Further, in the partial circuit generation device 14, by generating an addable partial circuit and adding the partial circuit,
Uniquely determines the redundancy created in the circuit. As a result, it is possible to add a partial circuit, and as a result, it is possible to estimate the circuit scale that will be reduced by removing the generated redundancy, and it is possible to quickly select an additional partial circuit that is effective in minimizing the circuit size. Further, the operation of redundancy detection is not required, the time required for the minimization is shortened, and the efficient minimization is realized.

In the partial circuit adding device 15, all the partial circuits generated by the partial circuit generating device 14 are input devices 1
It is added to the logic circuit input by 1.

The redundancy removing device 16 removes all the redundancy generated by the partial circuit addition to obtain a minimized logic circuit.

The storage capacity used in the present invention depends on the scale of the transition implication graph. The scale of the transition implication graph is a constant multiple of the scale of the logic circuit input by the input device 11. Furthermore, the time required for transforming the transition implication graph and generating the partial circuit is polynomial times the scale of the transition implication graph. As a result, the storage capacity required for the minimization and the calculation time do not exponentially increase due to the increase in the scale of the logic circuit input by the input device 11. Therefore, it can be minimized even for a large scale circuit.

The transition implication graph generation device 12 will be described with reference to FIGS. Transition implication graph generation device 1
2 generates a transition implication graph based on the multi-stage logic circuit input by the input device 11. First, what is the implication graph?
When the value of the wiring A in the circuit is Va (0 or 1), the value of the other wiring B is always Vb (0 or 1).
Is a graph expressing the implication. Here, when the circuit of FIG. 2A is input by the input device 11, the implication graph is as shown in FIG. Figure 2
In the implication graph of (b), the node Ao is shown in FIG.
Shows that the wiring A in the circuit has a value of 0 (the nodes when the wirings in the circuit have a value of 1 are omitted). Further, the edge 21 from the node Ao to the node Fo represents the implication that the value of the wiring F is always 0 when the value of the wiring A is 0 in the circuit of FIG.

Furthermore, the transition implication graph is a graph composed of an edge corresponding to the longest path of the implication graph and points at both ends of the path. The transition implication graph obtained from the implication graph of FIG. For example, FIG.
In (b), from Ao to edge 21, further edge 2
2. There is a longest path to Po and Qo via the edge 23 and the edge 23, respectively. In this case, the path of edge 21 and edge 22 is edge 31 in FIG.
3 is represented by an edge 32 in FIG. 3, and the nodes Ao, Po, and Qo at both ends are included in the graph of FIG. At this time, the node F located in the middle of the path in FIG.
o is not included in the graph of FIG. The graph thus created is the transition implication graph.

The transition implication graph transformation device 13 will be described with reference to FIGS. The transition implication graph transformation device 13 reduces the scale of the transition implication graph generated by the transition implication graph generation device 12. For example, FIG.
In the transition implication graph of, there is an edge from each of the node Ao, the node Bo, the node Co, and the node Do to the node Po and the node Qo. In this case, one intermediate node No. is newly generated as shown in FIG. 4, and these edges are converted so as to pass through this node No. This reduces the number of edges in the transition implication graph.

The partial circuit generator 14 will be described with reference to FIG. The transition implication graph transformation device 13 generates a possible partial circuit from the transition implication graph whose scale has been reduced. When the transition implication graph of FIG. 4A is input, the partial circuit generation device 14 generates the partial circuit of FIG. 4B. For example, from node Ao to node N in FIG.
In the partial circuit of FIG. 4B, the edge 41 up to o is represented by connecting the wiring A to the input of the AND gate G5 whose output is the wiring N. In addition, connection 4 from wiring N
3 and the connection 44 are respectively connected to the input of the AND gate having the wiring P as the output and the input of the AND gate having the wiring Q as the output.

The partial circuit adding device 15 will be described with reference to FIGS. The partial circuit obtained by the partial circuit generation device 14 can be added to the logic circuit input by the input device 11. For example, FIG. 5 is obtained by adding the partial circuit of FIG. 4B to the circuit of FIG. Taking an AND gate as an example, the wiring A can be connected to the input of an AND gate when the value of the output of the AND gate is 0 and when the value of the output of the AND gate is always 0. The relationship is used. In FIG. 5, when the value of any of the wirings A, B, C, and D becomes 0, the value of the wiring N becomes 0, and the values of the wirings P and Q become 0. Therefore, the above relationship is satisfied. You can see that it is done.

The redundancy removing device 16 will be described with reference to FIG. When a partial circuit is added by the partial circuit adding device 15, the existing connection from the wiring corresponding to the input of the partial circuit becomes redundant and can be disconnected. In FIG. 5, the connections 51, 52, 53, 54 can be disconnected. The connection 51 from the wiring A to the wiring F will be described as an example. When the value of the wiring A is 0, the values of the output wiring P and the wiring Q are set to 0 through the wiring N, so that the propagation of the value to the wiring F is unnecessary. Further, when the value of the wiring A is 1, it does not directly affect the value of the wiring F. Therefore, the connection 51 from the wiring A to the wiring F can be cut. Connection 51,5
Gates G1 and G2 are further cut by cutting 2, 53 and 54.
Becomes redundant, and the wirings F and G become redundant, so that the finalized minimized circuit is shown in FIG. This redundancy is uniquely determined by the partial circuit generation device 14.

[0025]

According to the present invention, since the storage capacity and the calculation time can be shortened, the large-scale logic circuit can be minimized. Furthermore, by using the transition implication graph, it is possible to provide a minimization capability and an efficient minimization device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a logic circuit minimization apparatus of the present invention.

FIG. 2 is a diagram showing a circuit example and an implication graph thereof.

FIG. 3 is a diagram showing a transition implication graph of the implication graph of FIG.

FIG. 4 is a diagram showing a modified transition implication graph of FIG. 3 and a partial circuit that can be added.

5 is a diagram showing a circuit in which the partial circuit obtained in FIG. 4 is added to the circuit in FIG.

FIG. 6 shows a minimized circuit.

[Explanation of symbols]

 11 Input Device 12 Transition Implication Graph Generation Device 13 Transition Implication Graph Transformation Device 14 Subcircuit Generation Device 15 Subcircuit Addition Device 16 Redundancy Removal Device

Claims (2)

(57) [Claims] 1. An input device for inputting a multi-stage logic circuit, a transition implication graph generation device for generating a transition implication graph showing a relation of values between wirings in the logic circuit input to the input device, and the transition. A transition implication graph transformation device that transforms the transition implication graph generated by the implication graph generation device to reduce its scale, and a logic circuit input to the input device from the transition implication graph transformed by the transition implication graph transformation device A partial circuit generating device that generates the maximum number of partial circuits that can be added to the partial circuit, a partial circuit adding device that adds the partial circuit generated by the partial circuit generating device to the logic circuit input to the input device, and the partial circuit And a redundancy removing device for removing redundancy of a circuit generated by adding a partial circuit in the adding device. Apparatus. 2. The implication graph is a graph representing the implication relationship that when the value of the wiring in the circuit becomes 0 or 1, the value of the other wiring always becomes 0 or 1. The logic circuit minimization apparatus according to claim 1, wherein the graph is a graph including an edge corresponding to the longest path of the implication graph and points at both ends of the path.