JPH09259173A - Designing method for logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a stable operation also for a logic circuit containing an asynchronous signal at the input, concerning a method for designing the logic circuit using a hardware description language. SOLUTION: The configuration of the logic circuit to be the object of design is described while using the hardware description language, and the logic circuit is constituted by applying this description to a logic synthesizing tool. Concerning the respective flip-flops of the constituted logic circuit (S31 and S37), upstream pathes are traced backward one by one and search is performed until reaching the input terminal or the other flip-flop (S32). Then, the flip-flop, in which the upstream path reaching the input terminal to be given an asynchronous signal exists, is registered as the processing object (S35 and S36). Concerning the registered flip-flop, processing of plural steps is performed for additionally inserting the other flip-flop to the preceding or following step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a logic circuit, and more particularly to a method of designing a logic circuit having a built-in flip-flop that operates in synchronization with a predetermined clock signal.

[0002]

2. Description of the Related Art In recent years, as a method of designing a semiconductor integrated circuit such as an LSI, a hardware description language (H
DL: Hardware Description Language) is used to describe the configuration of a logic circuit to be designed, and based on this description, a method of configuring the logic circuit to be designed by combining individual circuit elements is in the limelight. ing. This type of method, which is currently mainstream, is based on the so-called RTL.
In this method, the circuit configuration is described in a hardware description language of (Register Transfer Level), and this description is given to a logic synthesis tool to perform logic synthesis to configure a target circuit. Normally, the logic circuit thus configured is subjected to an optimization process regarding timing and area,
You will get the final logic circuit. Such a design method is widely used for designing a synchronous logic circuit.

[0003]

The above-described design method using the hardware description language is suitable for designing a synchronous logic circuit, but is unsuitable for handling an asynchronous signal. Therefore, when designing a logic circuit including an asynchronous signal by the above method, the designer takes the timing condition during actual operation into consideration and then deals with it by giving a predetermined timing constraint to the logic synthesis tool. ing. That is, for an asynchronous signal, the expected delay value for the clock signal is given as a timing constraint to the logic synthesis tool, and the circuit configuration is performed under this timing constraint. However, in an actual LSI, the asynchronous signal is not always input with a constant delay time with respect to the clock signal. Therefore, if the rising or falling time of the clock signal and the changing time of the asynchronous signal happen to coincide with each other or come very close to each other, the logic output of the flip-flop in the circuit becomes unstable, Normal circuit operation cannot be guaranteed.

Therefore, the present invention provides a method for designing a logic circuit using a hardware description language, which can realize a circuit design that enables stable operation of a logic circuit including an asynchronous signal in its input. The purpose is to do.

[0005]

[Means for Solving the Problems]

(1) A first aspect of the present invention is a method for designing a logic circuit incorporating a flip-flop that operates in synchronization with a predetermined clock signal, wherein a hardware description language is used to design a logic circuit to be designed. The stage of describing the configuration,
On the basis of this description, the stage of configuring a logic circuit to be designed by combining individual circuit elements, and the upstream paths of the individual flip-flops of the circuit elements constituting the logic circuit are reversed one by one. , Searches until it reaches an input terminal or another flip-flop, and performs signal tracking processing to register a flip-flop having an upstream path reaching an input terminal to which an asynchronous signal is given as a processing target. The step and the step of performing a multi-step process of additionally inserting another flip-flop in the preceding stage or the subsequent stage for the flip-flop registered as the processing target are performed.

(2) The second aspect of the present invention relates to the above-described first aspect.
In the designing method according to the above aspect, the input signal other than the clock signal is regarded as an asynchronous signal when performing the signal tracking process.

(3) A third aspect of the present invention is the above-described first aspect.
Alternatively, in the design method according to the second aspect, after performing the multi-stage processing, the optimization processing regarding the timing or the area is further performed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings. Generally, the synchronous logic circuit includes a large number of flip-flops, and each flip-flop operates in synchronization with a common clock signal. For example, in the D-type flip-flop 1 shown in FIG. 1, the input signal A is given to the input terminal D, and the output signal B is outputted from the output terminal Q, but the output signal B rises or falls. Will be synchronized with the clock signal given to the clock terminal CK.
Here, when the timing between the input signal A and the clock signal is predetermined, for example, when the input signal A always changes with a predetermined delay time with respect to the rising time of the clock signal, the input signal A is the clock signal. It is synchronized with the signal. As described above, when all the input signals are synchronization signals, no serious problem occurs even if the design method using the hardware description language described above is applied.

However, when the input signal A is a signal completely unrelated to the clock signal, that is, when the input signal A is an asynchronous signal with respect to the clock signal,
The operation of this flip-flop 1 may become unstable. That is, when the rising or falling time of the clock signal and the changing time of the asynchronous signal happen to coincide with each other or are very close to each other, a slight temperature change or voltage change causes a flip-flop. The logic output of 1 will change. In this way, if the logic output of each flip-flop forming the logic circuit becomes unstable, normal circuit operation is no longer guaranteed.

As a method for dealing with such a problem, a multi-stage process of flip-flops is known. For example, when the flip-flop 1 shown in FIG. 1 is connected to the subsequent stage of another flip-flop 2 which is exactly the same as the flip-flop 1 and the circuit configuration shown in FIG. 2 is adopted, even if the input signal A is an asynchronous signal. The output signal B of the flip-flop 2 becomes a synchronization signal having a stable logic output. Although the output timing of the output signal B is delayed by one clock by such a multi-stage processing, it does not affect the logical operation of the entire circuit. The present invention provides a method for automatically performing this multi-stage processing for a logic circuit having a large number of flip-flops only for necessary flip-flops.

FIG. 3 is a flowchart showing the processing procedure of the logic circuit designing method according to the present invention. First, step S
In No. 1, HDL description is performed. This work is performed by using a predetermined hardware description language (HDL:
Hardware Description Language) is used to describe the configuration of a logic circuit to be designed. For example, the circuit configuration may be described in a so-called RTL (Register Transfer Level) hardware description language.

In subsequent step S2, a logic circuit configuration process is performed. This process is a process of constructing a logic circuit to be designed by combining individual circuit elements based on the logic description created in step S1, and is usually automatically performed using a logic synthesis tool. Specifically, this process is composed of a logic conversion process for converting a logic description into a specific circuit element and a technology mapping process for applying the logic description to a desired technology. Therefore, detailed description is omitted here. FIG. 4 is a circuit diagram showing an example of the logic circuit 100 configured by this logic circuit configuration processing (only a part relevant to the processing description of step S3 described later is shown). The logic circuit 100 comprises flip-flops 11, 13, 15, 21, 23 and logic gates 12, 14, 16, 22, 24, 25.

The signal tracking process in the next step S3 and the multistage conversion process in step S4 are peculiar processing steps added in the present invention. The multi-stage process of step S4 is a process of converting the flip-flops into a plurality of stages based on the above-described principle. Specifically, the flip-flops to be processed are different from each other in the same flip-flop before or after. Is a process of additionally inserting. By this processing, a stable synchronization signal can be obtained as an output signal of a flip-flop that inputs an asynchronous signal. On the other hand, the signal tracking process in step S3 is a process for identifying the flip-flops that need the multi-stage process. Since the output signal of the flip-flop that receives only the synchronizing signal as the input signal is always a stable synchronizing signal, it is not necessary to perform the multi-stage processing. The flip-flop including the asynchronous signal in the input signal is sufficient for the multistage processing. Therefore,
The process for identifying the flip-flops that need to be subjected to the multi-stage process out of all the flip-flops forming the logic circuit created in step S2 is the signal tracking process in step S3.

The basic policy of the signal tracking processing in step S3 is to trace the input signal of each flip-flop to the upstream side and specify whether it is a synchronous signal or an asynchronous signal. That is. Then, with respect to the flip-flop having the input of the asynchronous signal, this is registered as the processing target of the multi-stage processing. Specifically, the individual flip-flops of the circuit elements that make up the logic circuit are searched one by one in the upstream path in reverse direction until they reach the input terminal or reach another flip-flop. ,
For the flip-flop having the upstream path that reaches the input terminal to which the asynchronous signal is given, the processing to be registered as the processing target of the multi-stage processing is performed.

FIG. 5 is a flow chart showing the detailed procedure of the signal tracking processing in step S3. Here, with respect to the logic circuit 100 shown in FIG. 4, the process shown in the flowchart of FIG. 5 will be described by taking the procedure of executing the signal tracking process as an example.

First, in step S31, one flip-flop is selected. The following processing is performed for this selected one flip-flop. here,
The following description will be continued on the assumption that the flip-flop 11 in the logic circuit 100 shown in FIG. 4 is selected first. In subsequent step S32, a process of searching one upstream path is performed until the input terminal or another flip-flop is reached. In general, there are often multiple upstream paths on the input side of a particular flip-flop. When there are a plurality of upstream routes in this way, in step S32, a search process is performed for one of the upstream routes. For example, for the flip-flop 11 of FIG. 4, after going up to the logic gate 12,
Although it will be branched into two, the search will be continued by selecting one of the branch routes to the upstream side. Here, the following description will be continued on the assumption that the logic gate 12 goes up to the flip-flop 13.

Thus, when one upstream path is searched and the input terminal or another flip-flop is reached, the search is completed there. In the case of the above example, the search for the upstream route is completed when the flip-flop 13 is reached. Here, the path of this flip-flop 11 → logic gate 12 → flip-flop 13 will be called the upstream path a.

Next, in step S33, it is determined whether the final reaching point is the input terminal or the flip-flop. In the case of the above example, since the flip-flop 13 is the final reaching point, steps S33 to S3 are performed.
We will proceed to 4. In this step S34, it is determined whether or not all upstream routes have been searched. In the above example,
Since another upstream path exists in the flip-flop 11, a negative determination is made in step S34, and again,
The process of step S32 is repeated.

In the processing of step S32, this time,
Flip-flop 11 → logic gate 12 → logic gate 1
The upstream path b of 4 → flip-flop 15 is searched. Since the final arrival point of the upstream route b is the flip-flop 15, the process of step S32 is executed again through steps S33 to S34. Then, this time, flip-flop 11 → logic gate 12 → logic gate 14 → logic gate 16 → input terminal T1
Is searched for. Since the final reaching point of the upstream path c is the input terminal T1, the process proceeds from step S33 to step S35, and it is determined whether or not the synchronizing signal is applied to the input terminal T1. In the logic circuit 100 shown in FIG. 4, the clock signal CLK is applied to the input terminal T1, and the clock signal CLK is a synchronizing signal as a matter of course. Therefore, a positive determination is made in step S35, and the process proceeds to step S34. It will be. If the signal applied to the input terminal T1 is an asynchronous signal, the process proceeds to step S36.

By this time, the flip-flop 1 has already been
With respect to 1, since the search has been completed for all the upstream routes a, b, and c, step S3
At 4, a positive determination is made, and the process proceeds to step S37. Here, it is determined whether or not all the flip-flops in the logic circuit 100 have been selected. In the case of the above example, a negative determination is made and the process returns to step S31. This is the first flip-flop you selected.
The process regarding 1 is completed.

Next, assume that the flip-flop 21 is selected in step S31. In a succeeding step S32, for this flip-flop 21, an upstream path d of, for example, flip-flop 21 → logic gate 22 → flip-flop 23 is searched. Since the final arrival point of the upstream path d is the flip-flop 23, the step S32 is repeated again through the steps S33 to S34. Therefore, it is assumed that the upstream path e of the flip-flop 21 → the logic gate 22 → the logic gate 24 → the input terminal T2 is searched as the next upstream path. Since the final arrival point of the upstream route e is the input terminal T2, steps S33 to S3
It will advance to 5. The input signal U is applied to the input terminal T2. Therefore, it is determined whether or not this input signal U is a synchronization signal. In order to make this determination, at the stage of step S1 or S2 in FIG.
For each input signal, the designer has a clock signal CL
It suffices to perform an operation of adding information for specifying whether the signal becomes a signal synchronized with K or an asynchronous signal. Here, the following description will be continued assuming that the input signal U is an asynchronous signal. In this case, the process proceeds from step S35 to step S36, and the process of registering the flip-flop as a multi-stage processing target is performed. That is, the flip-flop 21 is registered as the processing target.

When the registration process of step S36 is completed in this way, the process proceeds to step S37. That is, the processing for the flip-flop 21 is completed. In the example shown in FIG. 4, for the flip-flop 21, the flip-flop 21 → the logic gate 2
There is also another upstream path f of 2 → logic gate 24 → logic gate 25 →, but it is no longer necessary to search for this upstream path f. Since at least an input controlled by the asynchronous signal U from the input terminal T2 is given to the flip-flop 21, it has been confirmed at this point that the flip-flop 21 should be the target of the multi-stage processing, No further search for upstream routes is required.

In this way, all flip-flops in the logic circuit 100 are similarly processed. For example, the flip-flops 13, 1 shown in FIG.
The same processing is performed for 5 and 23.
In this way, when all the flip-flops are selected and the processing is executed, this signal tracking processing is completed. Finally,
Some of the flip-flops are registered as processing targets for multiple stages. In the multi-stage process of step S4 in the flow chart shown in FIG. 3, the multi-stage process may be executed for the flip-flops registered in this way. That is, for the flip-flop registered as the processing target, the completely same flip-flop is additionally inserted in the preceding stage or the succeeding stage. As a result, stable logic operation can be ensured even with a logic circuit including an asynchronous signal as an input signal.

After the final circuit elements are determined in this way, an optimization process is executed in step S5.
Examples of the optimization processing include timing optimization processing (change processing for enabling faster logic operation) and area optimization processing (change for further reducing the chip area and increasing the degree of integration). Process) is general, but the description of these optimization processes is omitted here.

In the above example, the designer sets whether each input signal is a synchronous signal or an asynchronous signal. However, when it is desired to simplify such setting work. In addition, all input signals other than the clock signal may be treated as asynchronous signals. In this case, step S35 in the flowchart of FIG. 5 is a process of determining whether or not the input signal is the clock signal. However, since input signals other than clock signals may be signals that are originally synchronized with the clock signal, in order to perform efficient design, it is necessary to set whether each input signal is synchronous or asynchronous. Is preferred.

[0026]

As described above, according to the logic circuit designing method of the present invention, since the flip-flop having the asynchronous signal input is subjected to the multi-stage processing, the design using the hardware description language is performed. Even if you do, you can ensure stable operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a D-type flip-flop 1.

FIG. 2 is a circuit diagram showing a circuit in which a flip-flop 1 shown in FIG. 1 is subjected to multi-stage processing and another flip-flop 2 is connected to a subsequent stage.

FIG. 3 is a flowchart showing a processing procedure of a method for designing a logic circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a logic circuit 100 configured by a logic circuit configuration process of step S2 in the procedure shown in FIG.

5 is a flowchart showing a detailed procedure of a signal tracking process of step S3 shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Flip-flop 2 ... Flip-flop 11 ... Flip-flop 12 ... Logic gate 13 ... Flip-flop 14 ... Logic gate 15 ... Flip-flop 16 ... Logic gate 21 ... Flip-flop 22 ... Logic gate 23 ... Flip-flop 24 ... Logic gate 25 ... Logic gate 100 ... Logic circuit A ... Input signal B ... Output signal CLK ... Clock signal T1 ... Input terminal T2 ... Input terminal U ... Asynchronous input signal af ... Upstream path

Claims (3)

[Claims] 1. A method of designing a logic circuit having a built-in flip-flop that operates in synchronization with a predetermined clock signal, the method including a step of describing a configuration of a logic circuit to be designed using a hardware description language. Based on this description, a step of configuring a logic circuit to be designed by combining individual circuit elements, and one upstream path for each flip-flop among the circuit elements configuring the logic circuit Each time it reverses, it searches until it reaches the input terminal or another flip-flop, and registers the flip-flop with the upstream path that reaches the input terminal to which the asynchronous signal is given as the processing target. Regarding the step of performing processing and the flip-flop registered as the processing target, another flip-flop is provided at the front stage or the rear stage. Design method of a logic circuit and having the steps of performing a plurality staged process of adding inserts flop, a. 2. The design method according to claim 1, wherein an input signal other than a clock signal is regarded as an asynchronous signal when performing signal tracking processing. 3. The method for designing a logic circuit according to claim 1, further comprising performing an optimization process regarding timing or area after performing a multi-stage process.