JPH0451367A - Synthesis device for logical circuit - Google Patents

Abstract

PURPOSE:To synthesize the logical circuits of high performance by providing a means which gives arbitrary delay time to the constitution element of an abstraction circuit, executing timing analysis at the stage of the abstraction circuit, and executing optimization so that the restriction of delay time is satisfied through the use of an analysis result. CONSTITUTION:A timing restriction 104 sets restriction delay time in the arbitrary point of a register transfer specification. A timing restriction setting/ violation detection part 105 fetches data on the type of the element of an initial abstraction circuit from a design data base part 103, calculates the delay time of the element and allocates it to the initial abstraction circuit generated in a design data conversion part 102, fetches the timing restriction 104 and inspects whether given timing restriction is realized or not. A logical synthesis part 106 analyzes a violation circuit detected in the violation detection part 105, develops the abstraction circuit to a concrete circuit, simplifies a redundancy circuit and allocates data to the circuit element.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an apparatus for automatically synthesizing logic circuits, and in particular to an apparatus for automatically synthesizing logic circuits based on timing constraints. Regarding equipment.

(Prior Art) With the development of logic synthesis technology, it has become possible to automatically generate a structural level circuit from a register transfer level circuit description.

However, when comparing the performance (especially in terms of operating speed) of logic circuits designed by experienced designers and automatically synthesized logic circuits, the manually designed one is superior. This is because a skilled designer determines the register clock so as not to satisfy the operating frequency of the circuit, and designs the logic circuit while constantly considering the critical path. In other words, they are well aware of what kind of structure the circuit should have to minimize signal delay time.

In addition, by using timing analysis tools, designers can now obtain detailed analysis results of signal delay times of logic circuits (for example, whether the path to and is the longest delay path or the least delay path). It could not be used until after the founder had completed the design of the desired logic circuit. Therefore, it was necessary to perform a timing analysis on the logic circuit after logic synthesis and manually repair the parts that violate the constraints considered by the GLFI.

On the other hand, in recent logic synthesis technology, after assigning library hardware components (library cells) to gate circuits, timing analysis is performed using the timing analysis means built into the logic synthesis system, and the results are If the timing constraints desired by the installer are not met, replace the slower hardware components with faster hardware components and run the timing analysis again to confirm that the timing constraints are met. The method used was to investigate the problem and repeat it until it was satisfied or reached its limit.

On the other hand, a method has also been considered in which timing information is stored in an abstract component that is a library that does not depend on the technology of the hardware component, and this is used during synthesis. Regarding this technology, JP-A-63-1
This is disclosed in Japanese Patent No. 55268.

However, since the number of inputs of abstract components is variable and the component itself has a bit width, it is necessary to register a huge number of components in the library according to the allowed bit width, and this method requires a large amount of recording. It needed capacity.

(Problem to be solved by the invention) As mentioned above, the conventional technology has a problem in that timing analysis cannot be performed unless the circuit is configured with components prepared as a parts library.

In addition, since the number of inputs and outputs is originally variable in abstract circuits converted from register transfer circuits, if all usable abstract circuits have delay times and create a library for each, the amount of data will be enormous and it will be difficult to understand. It has been completed.

The present invention has been made in view of these points, and its first objective is to create an abstract circuit using a delay time ratio (= I means) suitable for hardware having the same function but with a different structure. We would like to propose a device that can synthesize high-performance logic circuits by performing timing analysis at the stage of synthesis and using the resulting timing violation information before or during synthesis. .

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides a logic circuit synthesis device that automatically generates logic circuits, which generates logic circuits before or during synthesis. Use the abstract circuit created by [
, in order to perform timing analysis, we need a means to give an arbitrary delay time to the elements constituting the abstract circuit, and perform timing analysis using the given delay time to determine whether the timing constraints are satisfied. a means for detecting;
means for converting or synthesizing the abstract circuit into a logic circuit so that a timing constraint is satisfied using the detected timing analysis results; and a circuit for optimizing the delay time of a circuit that violates the timing constraint. and means for converting or synthesizing.

(Operation) According to the device of the present invention, any delay time can be assigned to the elements constituting the abstract circuit converted from the functional operation specification description, and this delay time can be used to provide timing before or during synthesis. Verification can be performed. Furthermore, using the results of timing analysis, abstract circuits can be converted or synthesized into logic circuits so as to satisfy delay time constraints, and optimization can be performed repeatedly, allowing high-speed synthesis of logic circuits.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a logic synthesis device according to an embodiment of the present invention.

Reference numeral 101 in FIG. 1 is an input section for a register transfer specification representing a functional operation specification, and is a functional block diagram showing a register transfer description or a schematic representation of the specification. 1 [ ] 2 is a design data converter (translator). This conversion part] 0
2 parses the register transfer description of the human resources department 101,
An initial abstract circuit faithful to the description is generated. In the case of a functional block diagram, network information and graphic information are extracted from the schematic diagram to generate an initial abstract circuit. 103 is a film type database section that stores network information of the abstract circuit. ]04 is a timing constraint input section, which allows a constraint delay time to be set at any point in the register transfer specifications.

Reference numeral 105 denotes a timing constraint setting and violation detection unit which, because the number of inputs and outputs of the abstract functional element generated by the translator unit 102 is not constant, inputs the type and number of inputs or bit width of the element of the initial abstract circuit from the design database unit 103. A delay time calculation unit (=J means, a means for taking in timing constraints from the input section 104, and a timing constraint obtained by jFj, which calculates and allocates the delay time of the element)
It consists of a critical path search means that verifies whether or not it is realized in abstract circuits or logic circuits before and during logic synthesis. ]06 is a logic synthesis unit that analyzes the violating circuit detected by the timing constraint violation detection unit 105, divides the circuit into optimization target circuits, further sets an optimization target value, and sets the optimization target value. Expand abstract circuits into concrete circuits, simplify redundant circuits, and
It consists of processing means for allocating circuit elements depending on technology. 107 is a design data conversion unit;
It is used to convert descriptions and generate schematic diagrams.
Specifically, the circuit information stored in the existing database is converted into a logical circuit (structural description or schematic diagram).

108 is an output section of the synthesized logic circuit.

FIG. 2 is a diagram illustrating the processing flow of the logic synthesis device explained in FIG. 1.

201 is a step of manually creating a register transfer description and timing constraints, and 202 is a step of analyzing the operation of the description to generate an initial abstract circuit. 203 is a step in which the delay time is calculated by #1 and assigned to the abstract circuit element. Step 204 is a step of calculating the delay time of the entire circuit using division (=1-digit delay time), detecting the critical path, and checking whether the timing constraints are observed.If the constraints are not observed, , displays the parts that violate the constraints in Revo-1 or schematically.In addition, for the paths that violate the timing constraints, develop and optimize them into faster circuits so that the constraints are realized. (205) Steps 203 and 20
4 is repeated to check whether the timing constraints are satisfied, and the synthesis is completed by allocating a node (206). The processing contents of each step will be explained in detail below.

Before that, the register transfer description will be explained.

In register transfer descriptions, facilities that are recognized as circuit elements (external terminals, internal signals, registers, memory, etc.)
operators, built-in functions (such as addition and subtraction), and processes that represent facility operations (such as asynchronous clearing of registers)
It is possible to describe and express state transitions. Hereinafter, facilities, operators, built-in functions, processes, and stage 1 will be referred to as abstract functional elements.

Here, the delay time of the abstract functional element will be explained. Logic synthesis ultimately expands abstract functional elements to logic elements (gates), performs optimization, and divides (=1) hardware library cells made of the desired technology into this. However, at the register transfer level This circuit is a functional level circuit, and is not necessarily a hardware-optimized circuit, that is, a circuit designed with consideration to the number of gates and the number of gates. It is not a good idea to allocate hardware cells to abstract functional elements.Also, even if the cells have the same function, the actual delay time will change by allocating cells with different speeds. The delay time of the signal propagation path is calculated by allocating real time to each abstract functional element of the transfer level circuit.
It is not appropriate to calculate. Therefore, in the device of this embodiment, the basic gate is used as a unit and the number of gate stages is used instead of the delay time. Also, in hardware NOR gate cells, the actual delay time varies considerably as the number of inputs increases (for example, a 6-person NOR has a delay time four times that of a 2-person NOR). Now, we will give the number of stages in consideration of the number of manpower.

Next, the processing of the delay time meter spread means (=J means) which is the sub means of the detecting section]05 in FIG. 1 will be explained.

First, in order to be able to search for the critical path even if some abstract functional elements are converted to concrete hardware cells during logic synthesis, the cells existing in the hardware cell library are The number of stages is calculated using the elements and stored in the delay information library. Regarding abstract functional elements at the register transfer level and abstract functional elements or logic elements generated during synthesis, the abstract functional elements are retrieved from the configuration R1 database unit 103, and the type, bit width, and number of inputs of the elements are set as variables. In step 17, the number of stages is calculated to 51 according to a delay model that assumes that they are expanded into a network consisting of typical abstract elements and logic elements during logic synthesis, and a delay model of the logic elements themselves.
Store in design database. Here, since the number of delay stages of the abstract functional element differs depending on the circuit after expansion of the abstract functional element, a plurality of delay models are prepared as well as means for calculating the number of stages. In addition, the number of delay stages once calculated in this process is saved in the work storage area together with the type of abstract functional element, the number of inputs, and the bit width, and the abstract functional element of the same type is retrieved from the film type database again. If so, perform hashing,
The data in the work storage area is extracted and allocated.

Here, the calculation of the number of stages will be explained by taking the 10-pin 2-manufactured full adder 6°O shown in FIG. 6 as an example.

If the adder is to be developed into a ripple carry type adder by logic synthesis, consider the delay model as being developed into the circuit shown in FIG. 6(b). Figure 6 (b
→The circuit consists of five 2-bit two-person full adders 601 to 6.
It is composed of 05. These are serially connected to the carry signal calculated in the lower bits (
601 to 605), the path from the input CI to the CO has the maximum number of delay stages. Also, the output data is 8:9>
(609) also has the same number of delay stages as the number of stages.

Therefore, when it is known that the maximum number of delay stages for a 2-bit, 2-manual adder is 6 stages, the maximum number of delay stages for a 2-bit, 2-manpower full adder is 30 stages.

The processing of the critical path search means in the detection unit 105 of FIG. 1 will be explained below using FIG. 3. now,
The critical path search area is between input registers, between input and output, between registers, and between register outputs.

Start processing (301.). Initial delay information, end point signal name, and timing constraint data (number of gate stages) information obtained by constants 11 in the facility and register transfer descriptions having human attributes are taken in (302). Extract network data from the design database that stores the results of translating the register transfer description (303
). Check whether the functional elements forming the network exist in the delay information library (304);
If it exists, the delay information is fetched from the library and allocated to the functional element (305). If it does not exist, the number of stages is calculated according to the delay model of the expanded circuit and allocated to the functional element (306).

Next, a path is traced from the input point toward the end point signal. Here, the input point refers to a facility that has a human power attribute or a constant attribute, and the end point refers to a facility that has data input or output attributes of the register. At this time, the data bus
For each of the control path (the path that can control data transfer using if and case in the register transfer description and creates the if and case condition signals) and the clock path (the path connected to the clock input of the register), The maximum number of stages to have is calculated while propagating. Regarding the clock path, after inputting the data to the register, the number of stages is calculated by 4 for the data bus connected to the output of the register. - The manually calculated number of stages of each element on the path is stored in the film type database (307). When the calculation of the number of stages for all end points is completed, the following processing is performed.

Next, using the timing constraint information assigned to the end point, we subtract the number of stages that the abstract functional element has from the end point toward the human input point, and then calculate the minimum number of delay stages required for the output of each abstract functional element (the most critical constraints) and stored in the design data path (308). Since signals between abstract elements are recognized as facilities in circuits at the register transfer level, delays in the paths themselves are also taken into consideration. Furthermore, the slack (the difference between the number of delay stages of the constraint just found and the number of stages from the human input of the path) is calculated and stored in the design database (309). Here, the slack is a negative value (
The point where the maximum delay is considered) exists on the temporal path.

After that, a path that does not satisfy the timing constraints is traced from the end point based on the slack value (3]-0) Furthermore, at this time, depending on the value of the control signal, a functionally unrealistic path may be selected as a critical path candidate. Note i
A path for which the conditions of f and case are satisfied without contradiction is defined as a true critical path, and the path information is stored in the film type database. Then, the information such as the number of stages, constraints, slack, etc. manually obtained from the output of each abstract element in the critical path 2 is stored in the film type database (31, 1), and the processing of the tree means is completed (31.2).

In addition, the critical path search means can simultaneously search for the critical path min (slack min) for the minimum delay stage [6] number constraint, as well as the critical path max (slack max) for the maximum delay stage number constraint given to the end point.

The logic synthesis unit 1 uses the critical path found by the critical path search means in FIG. 1 using FIG. 4 below.
The procedure of extraction of the circuit to be optimized (path to be optimized), selection of abstract functional elements on the path, expansion, and optimization processing performed in step 06 will be explained.

Here, the rule-based method used in the logical synthesis of the related civil engineering invention will be briefly explained.

After converting the register transfer description into an initial circuit using an I-translator, abstract functional elements are developed into functional elements or logical elements with a lower level of abstraction. At this time, depending on the degree of expansion, a circuit with a large number of gates but high speed, or a circuit with low speed but a small number of gates can be constructed, so a rule-based method is used to control the expansion. In other words, you can choose how to expand using rules. '' As mentioned above, the method of expansion can also be described by rules, but the selection control of expansion rules itself can be described by rules, and we will call these rules meta-rules. Furthermore, since optimization targeting abstract functional elements is impossible with methods using algorithms, rules are also used in this optimization.

In the following embodiment, a procedure for optimizing and synthesizing the critical path 1Tlax will be described. Note that unless otherwise specified, critical path will be used to mean critical path max, and slack will also be used to mean slack max. In order to synthesize so as to eliminate the critical path, the slack value calculated by the critical path search means should be set to zero, so the absolute value of the slack value is used as the optimization target value.

Processing is started (401). An optimized path and an optimization target value are determined from the critical path (402). The selection of the path to be optimized will be described later.

Next, a candidate abstract functional element to be expanded is searched for from the abstract functional elements of the optimized pathconi (403) (this will also be explained in detail later), and if a candidate exists, the number of delay stages when the abstract functional element is expanded. It is checked whether the value decreases (approaches the optimization target value) (404). It should be noted that since the delay time allocating means allocates a typical number of delay stages to the abstract functional element at the register transfer level, it can be seen that the delay time will be reduced if there is a rule for expanding to a faster abstract circuit. If the number does not decrease, the next candidate abstract functional element is extracted (403). If it decreases, the abstract element is expanded to an abstract element with a lower abstraction level (405). Then, the number of delay stages is assigned to the expanded abstract element using a delay information library.

If it is not in the library, calculate tl and allocate it (40
6). The number of stages is calculated by 81 for the network body of the abstract functional element after expansion (407), and the number of delay stages of the abstract functional element before expansion is compared with the number of delay stages calculated by 4, and the optimal path of the optimized path is calculated. Check whether the target value has been achieved (
408). If this is not achieved, the next candidate abstract functional element is extracted and repeated until there are no more abstract functional elements. After that, optimization [1] If the target value is not achieved, optimization is performed for the functional elements after expansion or for the functional elements at the end points of the path to be optimized (409). Check whether the above processing has been completed for all the paths to be optimized (4] O), and if it has been completed, perform a critical path search for the entire circuit to ensure that the critical path before expansion optimization synthesis has been resolved. Check whether there is one (4] 1). If the critical path has not been resolved, the process from step 402 onwards is repeated through a series of processes until the critical path remains unresolved (412). When the critical path is resolved or it is confirmed that it remains, expand the abstract functional elements of the network other than the abstract functional elements after the above expansion [7], and further optimize the number of elements (41 '3) Do not perform element number optimization processing on the circuit developed when solving this critical path. This concludes the delay time optimization synthesis process (41.4).

Next, the procedure for extracting the optimized path in step 4 [ ] 2 of FIG. 4 will be explained using FIG. 5. Start processing (501.). First, the path with the highest degree of risk (smallest margin) is selected from the slack value of the critical path l1laX discovered by the critical path search means (
502). It is checked whether the path overlaps with another critical path (503), and it is confirmed that this overlapping path is not the critical path min (504). If it does not overlap with the critical path min, select the value with the lowest risk (highest margin) among the slacks of this duplicate critical path (50
5). Then, the duplicate subpath is set as the optimal path, and the absolute value of the slack value with the lowest risk (largest margin) just found is set as the optimization target value (506).
. In addition, the target value of "Optimization 1 of non-rft ljJ subpaths" is the absolute value of the slack value of each critical path plus the target value of "Optimization 1 of duplicate subpaths" (507
).

However, this value is used when optimization of duplicate subpaths is successful. That is, when optimization fails, the unreached optimization target value of the duplicate critical path is added to the optimization target value of each subpath to be optimized, and the optimization target value is updated. If the critical path checked in step 503 does not match any other path, the entire extracted critical path is set as the path to be optimized, and an optimization target value is determined from the slack value (508). After dividing all the critical paths into optimized paths and finding the optimization 11 target value (509), this process is performed with medium+1. L, (51(]), interface data to logic synthesis, i.e. process 4
Proceed to 02.

Next, the procedure for selecting the second abstract functional element in step 403 of FIG. 4 will be explained.

First, (1) find the abstract functional element closest to the external output. This is to minimize the influence on other circuits caused by the conversion of the abstract element.

(2) Find the abstract functional element with the smallest fanout. This is because when an abstract element with a high fanout is converted to an abstract element with the same function but a smaller number of delay stages, there is a possibility that a path that has the converted abstract element as a node will be a path that violates the minimum number of stages. It is.

(3) Find the abstract functional element with the smallest fan-in. This means that when an abstract element with a large number of fan-ins is converted to an abstract element with the same function but a smaller number of delay stages, the path that has the converted abstract element as a node becomes a path that violates the minimum number of stages. This is because there is.

The priorities for (1) to (3) above are those that do not satisfy (2) and (3) and that satisfy (1). Select the abstract functional element with the smaller value. Since a rule-based system is used for this priority, it can be changed freely.

Here, an example of expansion of abstract functional elements in the logic synthesis unit 106 of FIG. 1 will be described using FIG. 6.

[Not shown in FIG. 6(a)] One order of expansion of the O-bit two-manual adder 600 will be described. FIG. 6(b) is a diagram in which a ripple carry 10-bit two-manual adder is constructed using five 2-bit adders (601 to 605). FIG. 6(C) shows one 2-bit adder (6(,) 6 ) and two 4-bit adders (607).

608) is used to configure a 0-bit two-manual adder. The number of gates of the 2-bit adder is 2 r) and the number of gate stages is three. On the other hand, the number of gates of a 4-bit adder is 4.
5, the number of stages is 5. Therefore, if the structure shown in FIG. 6(b) is adopted, the number of gates will be 100 and the number of keto stages will be 15. On the other hand, in the structure shown in FIG. 6(C), the number of gates is 110 and the number of gate stages is 12.

Now, when a request is made to develop a 10-bit adder on the critical path into a high-speed circuit, the circuit shown in FIG. 6(C) is selected and developed using the metal rule. On the other hand, if the 10-bit adder is not on the critical path, the circuit shown in FIG. 6(b) is selected and expanded using the metal rule.

Regarding the optimization of the abstract functional element after expansion, if a circuit like that shown in FIG.
By replacing it with one adder, the number of stages can be increased from 6 to 5.
The number of steps decreases, and the speed increases by one step.

Next, conversion from an abstract functional element to a logical element will be explained using FIG.

This will be explained using an example of a 1 adder (incrementer) of 8 bits. 8 written in register transfer level language
PIT's adder is translated into an abstract element called INC701. Then, when the logical configuration processing is started, the element I N C70] is EXOR(υ1
(alternative OR) 702, AND703, and N0T704.

Now, the circuit consisting of the logic elements shown in FIG. 7(b) and the circuit consisting of the logic elements shown in FIG.
Two circuits are considered: the circuit in Figure 7(b), where the carry calculation for each pin is performed by its own circuit, while the circuit in Figure 7(C) uses four circuits. It has a configuration using two 1-bit adders, and therefore uses the 4-carry result from the F-order 4 bits. The difference between the two expansion circuits is that the signal propagation delay in Fig. 7(b) is small (48 gates, 4 gate stages), whereas in Fig. 7(c), the signal propagation delay is small compared to the other circuits. It is characterized by a small number of gates (40 gates, 5 gate stages). When performing this expansion process based on rules, two basic expansion rules are prepared, and the I/O is placed on the critical path discovered by the critical path search means
An element called NC is used, and if a request for expansion is issued under the minimum delay condition, it will be determined by the metal rule and expanded to the circuit shown in Figure 7(b). This is developed into the circuit shown in Figure (c).

Furthermore, 4-person AND and 2-person AND are simplified rules.
If it is connected serially, if there is a method to convert it to 3 manual AND 2, 2 AD Figure 7 (b)
Is it possible that the circuit shown in FIG. 7(C) becomes the circuit shown in FIG. 7(C)?A flag is attached so that the serial combination of ANDs provided to minimize the number of gates is not simplified. By doing so, a structural circuit that satisfies the delay time minimization constraint can be generated.

The above embodiment is an example in which the circuit generated by the delay time minimization rule is not changed by the gate I/number minimization rule such as the above simplification rule. If the circuit is to be made smaller using the minimization rule, the flag may be turned off.

The process of searching and synthesizing a critical path will be explained below using a simple motif.

FIG. 8 is a functional block diagram before synthesis. 801-80
5 is an input terminal. Here, the input terminals 801 to 803 have a width of 4 bits. 806° and 807 are clock input terminals. Further, 808 is a 4-bit wide output terminal. 809 is a 4-bit 2-manual adder, and 810 is a 4-pill 2-manpower subtracter. 8]] is a comparator, 812 is a 4-bit 1 adder (INC), and 813 is a 4-bit 1 adder (INC).
It is a subtractor (DEC). 8] 4 and 815 are 1-bit and 4-bit registers, respectively, and 816 and 817 are 2-1 multiplexers. Furthermore, 818 is AND
819 and 820 are inverters. Further, 821 is an internal signal.

First, the functional elements and connection information of this circuit are written manually in a schematic or in a functional film type description language. This information is converted into circuit design data using a data conversion means. Now, this entire circuit is subjected to logic synthesis and constraints on delay time are given. Here, a maximum delay constraint stage count of 10 is given to the path ending at register R2 (815). Further, the maximum delay constraint stage number 19 is set to the output terminal G (808).

This setting can be done manually in a schematic by opening a text manual table with maximum delay time constraints for the data input terminal of the register symbol R2. The same applies to the output terminal G.

These constraints can be entered using commands without any schematic information.

Next, how to give delay information to each abstract functional element r. will be explained. It is important for film developers to be able to freely select or set delay times for functional blocks, but setting delay times each time a functional block is schematically input or a functional element is written reduces film efficiency. This is very bad, so automatic allocation is used. The delay time of an abstract functional element depends on the number of human resources and the number of bits, and more than one structural circuit can be considered for the same function, so here we assume a standard logic circuit with a good number of gates and delay time. and increment the delay time by 17. The numbers surrounded by dotted circles in FIG. 8 are the maximum number of delay stages for each functional block. Since the inverter has a smaller delay time than other logic gates, the number of gate stages is set to O here.

This is summarized in Table 1 below.

Table 1 Functional block type Number of delay stages ADD 6 SUB 7 COMP 5 MUX ITNC3 DEC3 REG 2 AND 11NV
O These are the types of abstract functional elements, the number of manpower, and the bit width of the number of manpower are taken out from the design space 1 data base, and calculated and assigned based on this information, and these are regenerated during synthesis. Save it in the work storage area because there is a possibility that it may be deleted.

Therefore, the critical path search process based on the delay time constraints set above will be explained.

Find the number of stages in the output of each abstract functional element from the input terminal. Input points A (802), B (803) C (8
04), D (805) is 0 stage, clock manually CK
i (806) has a delay time of 3 for the A-D input.
A stage delay is provided, and CR2 (807) has 16 stages.

The number of stages of data buses from input terminals A (802) and B (803) will now be explained. The value in the first row from the top of the dotted rectangle indicates the number of steps from the input.

The output of the subtracter (810) becomes 7 stages and the adder (809)
The output is 6 stages. Also, since the output of the MUX (816) has a large number of stages from the fake human power (810), it becomes 8 stages. On the other hand, the control input of MUX (81, 6) is CKi,
(806) has 3 stages and 2 registers R], and (81, 4) has 2 stages, resulting in 5 stages. Further, the output of MUX (81, 6) is a maximum of six stages. Therefore, this path takes eight stages from the data bus. Comparator (81,
The output of 1) has 13 stages, including the 8 stages of the path from F (821) and the 5 stages included in the comparator body. Further M.U.
The output of X (817) takes a value of 14 stages, which is larger than the 3 output stages of the pig path F (821) and the 1 adder (81, 2). Finally, the maximum number of stages of the path to the data input of register R2 (815) is 14 stages.

Next, the number of constraint stages (the value of the second stage of the rectangle of points) is calculated for the path whose end point is R2 (815). A maximum delay constraint of 10 stages is assigned to R2. The manual path to R2 comes from MUX (817). M.U.
A control signal 822 manually input from the right side of X represents a condition when it is false, and a control signal 823 represents a condition when it is true. M
The signal manually inputted from the left side of the UX (817) is a data signal and corresponds to the control signal manually inputted from the right side. Now M
The constraints on UX data and human power F (821) are 9 stages. Here, since F has a fanout of 2 or more, the original number of delay stages for the output of F cannot be determined. Therefore, when examining the constraints of the data bus of the true input of MUX (81, 7), it becomes 9 stages as in the case of false, and the INC
(8) Since 2) has three stages, the input to INC is six stages. This path ends here because it has reached the output of the register for which the end point has been specified. So MUX (817)
Find the constraint number of stages for the control signal path. Each MUX has nine stages of control input terminals. The number of stages at the output terminal of the comparator (81, 1) is nine, without considering the delay caused by the inverter of the false path of the MUX. Then, the number of stages at the input terminal of the comparator is calculated by four. Since the number of delay stages of the comparator is 5, the output of the input F (821) is smaller than the 9 stages calculated by 4 earlier, and the constraint is set to the 4 stages found just now. Similarly, the outputs of the adder (809) and the subtracter (81, 0) are 3 stages each, and since the number of delay stages of the subtracter (810) is 7 stages, A (802) and B (803) are respectively -
There will be 4 stages. On the other hand, in response to the control input of MUX (816), the output of register R1 (814) is 3 stages, and the clock power CK1 is calculated by subtracting the number of delay stages from the clock power of registers R1, (81, 4) to the data output. (8
06) is one stage.

Here, the sludge (constraint number of stages - number of stages from the starting point) is determined. The value in the third row of the three-column rectangle indicated by the dotted line is the slack value. If the negative value of this sludge value is traced from R2 (815), this becomes the critical path. In this motif, the -4 path is the most dangerous path,
Next is the -3 pass.

Similarly, for the output G (808), the manual power CK2
The number of stages from (807) is input A (802), B (8
03), has a delay of 16 stages with respect to E (801), so the manual clock of register R2 (81, 5) has 16 stages, and the data output of R2 has 18 stages. Further, the output terminal of the DEC (813) becomes 21 stages, and finally the output G (808) becomes 21 stages. Next, since the output G has 19 stages of constraints lj, DEC(81,3
) becomes 16 stages after subtracting the 3 stages of delay stages that the DEC itself has. Further, by subtracting the number of delay stages from the clock input to the data output of the register R2, the clock input CK2 (807) becomes 14 stages. Sludge is -2
Then, the critical path is CK 2- R2-DEC-
It becomes the pass of G.

Next, a method for selecting an optimization path will be explained.

The path with the highest degree of risk is selected from the slack values of the critical paths. The paths with the highest degree of risk will be shown based on the constraints given to R2's data manpower. cpl, 1 and c
pl,,2 is a critical path with -4 sludge, c
p2. ] and cp2.2 are critical paths with -3 sludge, and cp3°] are critical paths with -2.

Optimization target values for each critical path are shown as absolute values of slack values in targets 1 to 3. Combining the above two results, we get the following Table 2.

(Left below) cpl, 1:A Table 2 SUB-MUX COMP -MUX-R2 CI) 1. 2:B SUB MUX COMP MUX-R2 5lackl: targetl:4 cp2.1 ・A MUX-R2 cp2. 2: B -ADD MUX-R2 s 1 a Ck 2 : -3targ
et2:3 A D D MUX MUX COMP COMP cp3.1: CKI MUX OM P -MUX-R2 slack3 knee 2 target3:2 Now, if we focus on cpl,,i, this means that the part that overlaps with all other critical paths This is designated as an overlapping path oVp1. Optimization 11 The target value is 2 (otl) because the absolute value of the slack with the lowest risk among all critical paths is taken. Also, cpl-, i is cp
Both 1 and 2 overlap, and this is designated as ovp2. The optimization L1 target value is targetl-otl, which is 2 (ot2).

ovp 1 :MUX-F-COMP-MUX-R2o
tl:2 ov p2: SUB-MUX ot22 Next, focusing on cp2,1, since the overlapping path ovp1 has already been processed, the overlapping path ovp3 with Cr2,2 is set as the path to be optimized, and optimization]-1 The target price ov3 is 1 (
target2-otl).

For c p 3゜1, it becomes a candidate for oppl or the lotus to be optimized, but the target value opl is 0 (target3
-otl), so it was excluded from the candidates.

ov p 3 : ADD-MUX ov3:1 opp 1 : CKI-R1-MUXapl: 0 However, for 0r) p], the optimization target value becomes zero only when optimization can be realized with ovpl.

Next, an optimization method applied to the optimized path ovpl will be explained.

The method to be described now is one in which a proportionate optimization target value is shared among a plurality of functional elements on the path to be optimized. On the other hand, it can also be realized by a method of assigning the maximum optimization target value to a certain functional element of the bus to be optimized and realizing the target value with the minimum number of expansions.

The cell L7 selects an abstract functional element with a smaller fan error I, and the target element is MUX817. Then, it is checked whether there is a speeding-up rule regarding the MUX development method, and since there is no current rule to develop the speed-up circuit (in this embodiment, it is assumed that there is no such rule), the next candidate is searched.

Furthermore, when an abstract functional element with a small fan area i is selected, COMP (81, 1) is selected as a candidate. So COM
Will it be faster after expanding P: J! Since it is true that it is better to do so, we will actually develop it. The circuit after expansion is shown in 9th
As shown in the figure. Then, the number of delay stages is given to each functional element after expansion. When calculating the number of stages of the partial circuit after expansion, it is 4.
The target value of ``optimization 1'' was achieved by one step.

However, EXOR (901) is a 2-stage, 4-person powered N0R (90
2) has two stages. However, the optimized path ovpl
Since the optimization i〒1 target value is 2 stages, it cannot be achieved with just the two-fold expansion, so I will search for the next candidate, but
MUX(81,6) is also impossible to perform optimization for the reasons stated in the second paragraph. For this reason, the number of delay stages between functional elements is optimized for the circuit after COMP is expanded, but as shown in FIG. 9, there is no room left for optimization, so the path to be optimized is expanded.

Optimize [1 Calculate the target value for the optimized path 0Vp2. Since the target value of "Optimization 1 of duplicated critical path ovpl" could not be achieved, the optimization target value of this optimization pass increases accordingly. The original optimization l' target value is 2 stages, but now the unrealized optimization of OVPL [1 target value and 1 stage is added, resulting in 3 stages. So when I search for optimization deployment candidates, SUB
(810) is selected, and when I check whether there is a rule to expand to the speed-up circuit, I find that it exists.
is developed into a high-speed circuit. Here, it can be expanded to a circuit with 5 delay stages (see Figure 10, 1001 is a 4-bit full adder and the number of delay stages is 5). Since there are no other functional elements in 0vp2 that can be optimized and expanded, the circuit after expansion is optimized between functional elements, but since there is no room left for optimization, the critical path cp1.1 and cps, 2
This means that he could not achieve the optimization 11 target value of 4 and could only earn 3 steps. Similarly, the optimization target value for ov p 3 is 2 stages, and the ADD of "pass" - will only be a minimum of 5 stages after expansion, so optimize the critical path cp2.1, cp2゜2! -1 stage of the target price cannot be realized, and the risk level of 1 stage remains. Furthermore, since the optimization target value of the duplicate critical path could not be realized, path opp1 becomes an optimized path with one stage of optimization target value, or M
Nothing is done because there are no optimization optimization candidates such as UX or REG. Therefore, one level of risk remains for the critical path cp3.1. Also, an attempt is made to see if it is possible to optimize the end points of each path to be optimized, but this is not possible in this embodiment because the paths to be optimized are separated by a MUX (816). According to this embodiment, the maximum number of delay stages is 14 to 1.
Reduced to 1 stage.

Although this embodiment has been described assuming that the number of delay stages in the circuit after expansion is known, if it is unknown, it is necessary to calculate the number of stages in the circuit after expansion. Furthermore, if the number of delay stages is optimized between circuits after deployment, the critical path search means again checks whether the critical path before deployment has been avoided, and repeats this process until all functional elements on the second critical path are deployed. .

[Effects of the Invention] As explained below, according to the apparatus of the present invention, timing verification can be performed at the abstract circuit level with a small memory capacity.
It becomes possible to determine whether timing specifications are met before synthesis. In addition, there are three ways to generate faster circuits during circuit expansion and optimization by using the delay time allocated to abstract circuits. This has the effect of realizing a circuit that satisfies the delay time constraints more than when optimization alone is used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of a logic circuit synthesis apparatus according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the processing flow of logic synthesis in an embodiment of the present invention, and FIG. A diagram illustrating the processing of the critical path search means in an embodiment of the present invention. FIG. FIG. 5 is a diagram explaining a method for extracting an optimized path from a critical path in an embodiment of the present invention. FIG. FIG. 7 is a diagram explaining the expansion of abstract functional elements in an embodiment of the present invention. FIG. 8 is a diagram explaining the conversion of an abstract functional element into a logic element in an embodiment of the present invention. FIG. 9 is a functional block diagram of a simple motif used to explain path search and synthesis processing; FIG. 9 is a diagram explaining the conversion of a comparator into a logic element in an embodiment of the present invention; and FIG. FIG. 2 is a diagram illustrating the expansion of a subtracter in an embodiment of the present invention. 101. Register transfer specification manual section] 04. Timing constraint input section 105 - Timing constraint setting and violation detection section 111 section 106
Logic synthesis section 108 Output section of logic circuit

Claims (2)

[Claims] (1) In a logic circuit synthesis device for automatically generating a logic circuit, the abstract circuit is configured to perform timing analysis using the generated abstract circuit before or during synthesis. means for giving an arbitrary delay time to an element, means for performing timing analysis using the given delay time and detecting whether a timing constraint condition is satisfied, and using the detected timing analysis result. means for converting or synthesizing the abstract circuit into a logic circuit so that timing constraints are satisfied; and means for converting or synthesizing the circuit to optimize the delay time of a circuit that violates the timing constraints. A logic circuit synthesis device characterized by: (2) The circuit conversion or synthesis means for delay time optimization analyzes the circuit violating the constraints detected by the timing analysis means, divides the circuit into optimization target circuits, and divides the circuit into optimization target circuits. Set the optimization target value to
2. The logic circuit synthesis apparatus according to claim 1, further comprising means for converting or synthesizing the circuit according to the optimization target value.