JP2925160B2 - Logic synthesis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a logic synthesis method for generating a logic circuit from an operation description or a functional diagram of a logic circuit to be designed. The present invention relates to a logic synthesis method for generating a technology-dependent logic circuit by assigning an existing logic element to a dependent circuit.

(Prior Art) With the enlargement of digital systems, various logic synthesis systems have been developed for the purpose of improving design efficiency. For these, input an operation description of a logic circuit to be designed or a technology-independent circuit drawing called a functional diagram, and input a real logic element (an element registered in a library used by a user. ) Is generated.

Hereinafter, a conventional logic synthesis method will be described with reference to FIGS. 5 to 10. FIG.

First, an operation description and a functional diagram of a logic circuit to be designed are input, and a technology-independent circuit is generated. For example, the fifth
The figure is an operation description in the case of designing a circuit that “controls data to be output to Z by the value of a 2-bit signal C”. In the description, DECODE is a function representing a decoding function of "set 1 to the n-th bit (DECODE (C) <n-1>) of the output when the value of argument C is n". From this description, for example, a technology-independent circuit as shown in FIG. 6 is generated. This circuit includes an abstract selector 31 and an abstract decoder 32, and is configured to select the inputs D1 to D4 of the abstract selector 32 by the output of the abstract decoder 32. As described above, the technology-independent circuit is generated by a macro element having functions such as an adder, a selector, and a decoder, and a primitive logic gate such as AND / OR having an arbitrary input. Hereinafter, the above-described macro elements are collectively referred to as an abstract function module, and are respectively referred to as an abstract adder, an abstract selector, an abstract decoder, and the like. The above-described primitive logic gates are hereinafter collectively referred to as abstract logic gates, and are respectively referred to as abstract AND gates and abstract OR gates.

Next, adders, selectors, and technology-independent circuits
And an abstract function module such as a decoder is developed into an abstract logic gate such as AND / OR, and optimization processing such as deletion of redundant logic is performed. For example, the abstract selector 31 and the abstract decoder 32 shown in FIG. 6 are expanded into abstract AND gates 41 to 48, an abstract OR gate 49, and abstract NOT gates 50 and 51, as shown in FIG. . Then, an abstract AND gate merging rule as shown in FIG. 8 is applied to the abstract AND gates 41 to 48, and further converted to a circuit consisting only of abstract NAND gates based on a conversion rule as shown in FIG. 7 (b) is obtained. In this way, redundant logic is eliminated.

Finally, a real element registered in the library is assigned to a circuit consisting of only the abstract logic gate. For example, when a four-input multiplexer allocation rule as shown in FIG. 10 is applied to the circuit pattern of FIG.
Are eventually matched, the circuit of FIG. 7 is eventually replaced by the real element MUX41. As a result, a technology dependent circuit as shown in FIG. 11 is finally obtained.

As described above, in the conventional logic synthesis method, all the abstract function modules are developed at the level of abstract logic gates such as AND / OR, NAND, and NOR to generate a technology-independent circuit consisting of only abstract logic gates. Is searched for a circuit pattern that is logically equivalent to a real element in the library, thereby allocating the real element.

By the way, in such a logic synthesis method, a search time of a circuit pattern for allocating a real element is determined by the number of gates constituting high-performance elements such as an adder, a selector and a decoder. For example, the pattern of FIG. 10A equivalent to the MUX 41 has 7 gates, the pattern of FIG. 10B has 15 gates, and the pattern of FIG. 10C has 13 gates. Therefore, there is a problem that it takes time to search for a circuit pattern.

Further, as shown in FIG. 10, the type of circuit pattern that is logically equivalent to one high-performance element is not limited to one type, and therefore, the search for circuit patterns must be performed for all types of patterns. There was also a problem that it took more time. There is also a problem that it takes time and effort to create an assignment rule for all of these patterns.

Furthermore, in the above method, since the logic optimization processing is applied after the abstract function module in the technology-independent circuit is expanded into the abstract logic gate, the circuit pattern immediately after the expansion is deformed and should be originally assigned. In some cases, high-performance devices were not assigned. As a result, for example, the multiplexer element MUX41 is not assigned and “NAND
There is also a problem that a circuit whose function is difficult to grasp, such as a "multiplexer circuit composed of only elements", is generated.

(Problems to be Solved by the Invention) As described above, in the conventional logic synthesis method, it takes a long time to search for a circuit pattern at the time of allocating high-function elements, and the quality of allocating high-function elements is reduced. there were.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and has developed a logic synthesis method capable of allocating existing high-performance elements such as an adder, a selector and a decoder at a high speed and generating a high-quality circuit. The purpose is to provide.

[Structure of the Invention] (Means for Solving the Problems) A logic synthesis method according to the present invention relates to a logic synthesis method for generating a technology-dependent logic circuit by allocating real elements to a technology-independent circuit. A feature element assigning means for directly assigning an existing function element to the included abstract function module before being expanded into the abstract logic gate is provided.

More specifically, the logic synthesis method according to the present invention includes a functional element existing in an abstract function module before being developed into an abstract logic gate, which is included in a technology independent circuit describing a logic circuit to be designed. Means for directly assigning an abstract function module which is not assigned by this means to an abstract logic gate, and means for expanding the abstract logic gate expanded by this means and the abstract logic gate included in the technology independent circuit. It is characterized by comprising at least means for performing an optimization conversion process for deleting redundant logic, and means for assigning a real element to an abstract logic gate optimized and converted by this means.

(Operation) In the present invention, in the logic synthesis process, an existing high-functional element is directly assigned by a functional element assignment unit without expanding an abstract functional module in a technology-independent circuit into an abstract logical gate such as AND / OR. Since assignment is performed, gate level matching becomes unnecessary, and the assignment process can be executed at high speed. In addition, since the abstract function modules can be assigned real elements while maintaining one unit, it is possible to prevent allocation quality from deteriorating due to unnecessary circuit pattern deformation.

(Example) Hereinafter, an example of the present invention is described based on an accompanying drawing. FIG. 1 is a block diagram showing the configuration of a logic synthesis system according to one embodiment of the present invention.

The logic circuit data storage unit 11 stores a network-like data structure that describes the components of the logic circuit and their connections. In the logic circuit conversion rule storage unit 12,
Stores high-function element allocation rules, abstract logic gate expansion rules, optimization conversion rules, and real element allocation rules, which will be described later. The high function element allocating unit 13 extracts the abstract function module from the logic circuit data stored in the logic circuit data storage unit 11 and executes the high function allocation rule according to the high function element allocation rule in the logic circuit conversion rule storage unit 12. I do. The abstract logic gate expansion unit 14 executes a process of expanding an abstract function module in the logic circuit data to which no particularly high-performance element is assigned according to the abstract logic gate expansion rule stored in the logic circuit conversion rule storage unit 12. . The optimizing conversion executing unit 15 executes an optimizing conversion process on the circuit part based on the abstract logic gate in the logic circuit data in accordance with the optimizing conversion rule such as redundant logic deletion stored in the logic circuit conversion rule storage unit 12. I do. The real element allocating unit 16 converts the logic circuit data into a circuit or the like consisting of only an abstract NAND gate, and then converts the real element allocation rules (for example, 2 inputs, 3 inputs and 4 inputs) stored in the logic circuit conversion rule storage unit 12. The real element allocation process is executed in accordance with an allocation rule other than the high function element such as the input NAND element. The execution control unit 17 includes these units 13 to 16
Control the boot order.

In the above configuration, consider the case where a circuit as shown in FIG. 6 is stored in the logic circuit data storage unit 11 now. This circuit is a technology-independent circuit having a function of selecting and outputting any one of D1 to D4 (all 1 bit) to Z according to the value of a 2-bit control signal C. It is generated from the operation description as shown in FIG. DECODE in the description is "argument C
Is n, the n-th bit of the output (DECODE (C) <n−
1>) is set to "1"). The circuit in FIG. 6 includes an abstract selector 31 and an abstract decoder.
32. In FIG. 6, C <1: 0>
Represents a 2-bit signal having bits 1 and 0.

FIG. 2 is a flowchart showing the operation flow of the system of this embodiment.

That is, first, in step S1, the execution control unit 17 of FIG.
By activating the high-functional element allocating unit 13, the process of allocating the real high-functional element to the abstract functional module is executed. Here, for the sake of simplicity, it is assumed that the existing high-performance elements are only 2-input, 4-input and 8-input multiplexers. In this case, for example, a rule as shown in FIG. 3 is stored in the logic circuit conversion rule storage unit 12 as a high function element assignment rule. According to this rule, a 4-input multiplexer MUX41 is assigned to an abstract function module, and the control input of an abstract selector having 4 data inputs is the output of a 2-bit abstract decoder as shown in FIG. The rule is to find a circuit pattern and convert it to a circuit consisting of the MUX 41 as shown in FIG. Here, assuming that the bit width of the input data of the abstract selector is n, n MUXs 41 are allocated.

The high function element allocating unit 13 executes a processing algorithm as shown in FIG. 4 using such rules. Sixth
When this algorithm is applied to the circuit shown in the figure, first, in step S11, the abstract selector 31 is extracted, and the process proceeds to steps S12, S13, and S14. Here, since k = 4, the process proceeds to step S15, and the allocation rule of the MUX 41 in FIG. The connection relationship between the abstract selector 31 and the abstract decoder 32 in FIG.
Since the application of the above rule is successful and n = 1 since it matches the circuit pattern of FIG.
A circuit including the MUX 41 is generated. As a result of this processing, the abstract selector no longer exists in this circuit, and the processing ends through steps S11 and S12.

Next, in step S2 of FIG. 2, the execution control unit 17 activates the abstract logic gate developing unit 14. As a result, the abstract logic gate development unit 14 uses the abstract logic gate development rules in the logic circuit conversion rule storage unit 12 to develop the abstract function module into abstract AND / OR gates. The abstract function module to be developed here is an abstract function module which remains without successfully allocating the high function element. Therefore, in FIG. 11, since there is no abstract function module, the state of the circuit does not change.

Further, the execution control unit 17 activates the optimization conversion execution unit 15 in step S3 of FIG. 2, and executes the real element allocation unit in step S4.
Start 16 As a result, a circuit consisting of only real elements is finally generated. Of course, even in this case, the circuit shown in FIG. 11 is a circuit composed of only existing elements, so that even after these processes, the state of the circuit does not change. Therefore, the circuit of FIG. 11 is finally generated.

As described above, according to the present embodiment, by examining the possibility of high-mechanism element allocation for expanding an abstract function module into an abstract logic gate, high-function elements can be allocated at high speed. In fact, the multiplexer MUX4 shown in FIG.
In the assignment of 1, it is only necessary to search for a circuit pattern composed of two elements and 10 connections of an abstract selector and an abstract decoder as shown in FIG. On the other hand, in the conventional method in which the high-performance elements are allocated after the abstract function module is expanded into the abstract logic gate, for example, in the case of the pattern composed of the abstract NAND gate in FIG.
A complicated circuit pattern consisting of book connections must be searched. Therefore, it takes time to search. Moreover, since the patterns shown in FIGS. 10B and 10C can be considered as a logically equivalent pattern to FIG. 10A including the abstract NAND gate,
It is necessary to search for these patterns, and the processing time is further increased. Incidentally, since FIG. 10B is composed of 15 elements and 27 connections, and C is composed of 13 elements and 25 connections, it takes more time to search than in the case of FIG. 10A.

Further, when the optimization processing or the like is performed after the abstract function module is expanded into the abstract logic gate, the circuit immediately after the expansion may be deformed, and may not match the pattern of FIG. As a result, in the conventional system, a multiplexer element is not assigned to a circuit having a multiplexer function, and a problem often occurs that a circuit whose function is difficult to grasp is generated. However, according to the present embodiment, an abstract function module does not exist. Since a high-performance element is assigned at the stage of performing, a high-quality circuit using function information of the circuit can be generated.

The present invention is not limited to the embodiments described above. For example, the system of the present invention and the conventional system may be used together. That is, the high-performance element allocating unit 13 allocates the high-performance device at the stage where the abstract function module exists, and the real device allocating unit 16
A method is also conceivable in which a pattern is searched for a circuit consisting only of abstract logic gates, and a circuit using high-performance elements as much as possible is generated by allocating high-performance elements. In this case, it is possible to generate a circuit of higher quality using a high-performance element. Further, in the above embodiment, the logic circuit conversion rules are provided as an independent rule base from each of the units 13 to 16.
It may be incorporated in

[Effects of the Invention] As described above, according to the present invention, before an abstract function module such as an abstract adder, an abstract selector and an abstract decoder in a technology-independent circuit is developed into an abstract logic gate such as an AND / OR. In the step of allocating real high-performance elements to the abstract function module, the search cost of the circuit pattern required for the allocation is significantly smaller than the conventional method of searching for a circuit pattern composed of primitive gates. As a result, a circuit including a high-performance element can be synthesized at high speed.

Also, instead of the circuit stage consisting of the abstract logic gates after the transformation such as the optimization process is performed, the actual function element is directly assigned to the abstract function module in the stage where the abstract function module exists, so that the circuit It is possible to generate a high-quality circuit that focuses on the functions described above.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic synthesis system according to one embodiment of the present invention, FIG. 2 is a flowchart showing an operation flow of the system, and FIG. 3 is a diagram showing a high function element assignment rule in the system. , FIG. 4 is a flowchart showing an algorithm for allocating high-performance elements in the system, FIG. 5 is a diagram showing an example of an operation description of a circuit to be designed, and FIG. 6 is a technology-independent circuit generated from the description in FIG. FIG. 7 (a) is a diagram showing a circuit obtained by expanding the circuit of FIG. 6 into abstract logic gates, and FIG. 7 (b) is an optimization process for the circuit of FIG. 7 (a). FIG. 8 shows a circuit obtained by applying
FIG. 9 and FIG. 9 show examples of optimization rules. FIG. 10 shows rules for allocating real elements to a circuit pattern composed of abstract logic gates. FIG. 11 shows the dependence on the technology to which real elements are allocated. It is a figure showing a circuit. 11: Logic circuit data storage unit, 12: Logic circuit conversion rule storage unit, 13: High function element allocation unit, 14: Abstract logic gate development unit, 15: Optimization conversion execution unit, 16: Real Element allocator, 17 ... Execution controller.

Claims (2)

(57) [Claims] A means for directly assigning a real functional element to an abstract function module before being developed into an abstract logic gate, which is included in a technology independent circuit describing a logic circuit to be designed; Means for expanding an unassigned abstract function module into an abstract logic gate; and optimizing conversion processing of at least redundant logic deletion for the abstract logic gate expanded by this means and the abstract logic gate included in the technology independent circuit And a means for allocating a real element to the abstract logic gate optimized and converted by the means. 2. A logic synthesis method in which a real element is assigned to a technology-independent circuit to generate a technology-dependent logic circuit, wherein an abstract function module included in the technology-independent circuit before being expanded into an abstract logic gate is provided. A functional element allocating means for directly allocating a functional element existing in the logic synthesis method.