JP2664946B2 - Logic circuit test pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A test pattern generation device for generating a test pattern of a logic circuit, which generates a test pattern at high speed by propagating to an external output and setting an external input at a macro element level such as a counter. In addition to selecting the macro element to be tested from the logic circuit, focusing on the data path, the symbol value at the input of this macro element is A symbol value allocating unit for allocating and assigning the output value of this symbol value to an output while focusing on the function of the macro element; and transmitting the assigned input and output symbol values to an external output and a A propagation / setting processing unit for setting, and a concrete pattern for the symbol value propagated / set by this propagation / setting processing unit. And a pattern embodying unit that generates a test pattern by substituting the test pattern. A test of the logic circuit can be performed using the test pattern generated by the pattern embodying unit.

[Industrial applications]

The present invention relates to a test pattern generation device that generates a test pattern for a logic circuit. Recent advances in LSI technology have made it possible to integrate large-scale circuits into one chip. However, in order to increase reliability, high-quality test patterns have been added to tests performed before product shipment to reduce manufacturing defects. It is desired to surely find a chip to have.

[Problems to be solved by conventional technology and invention]

The essential operations for generating an automatic test pattern are, as shown in FIG. 6 (a), an operation for propagating the influence of a fault to an external output terminal and an external input terminal for setting conditions for transmitting the effect to the outside. Operation.

Conventional automatic test pattern generation targets a gate-level circuit, defines a D-cube with an extended truth table, for example, as shown in FIG. 6 (b) for each gate type, and implements a propagation / setting operation. Like that. Here, in addition to the normal “0”, “1”, and “X (undefined value)” as truth values, a logical value D that is “0” when a fault exists and “1” when no fault exists. To clearly express the effects of the failure. Then, assuming a fault at one place in the circuit, a cube is applied to each gate, and an input value (test pattern) that causes the effect of the fault to propagate to an external output may be calculated.

However, when the circuit scale increases and the complexity increases, such as VLSI, (1) the problem that the calculation time increases, and (2) only gate-level circuits can be applied. There are problems that cannot be helped.

(1) Problem of increase in calculation time: Conventionally, a D-cube as shown in FIG. 6 (b) is applied at a gate level to a logic circuit to be tested at a gate level, and it is assumed that one fault in the circuit occurs. However, since an external input value to be propagated to an external output is calculated, the calculation time exponentially increases as the number of gates increases.

(2) A problem that can only be applied to a gate-level circuit and cannot be used for design for testability: This is a conventional test pattern generation target for a gate-level circuit, and the entire circuit is tested until the logic design is completed. Since the easiness cannot be determined, if it is determined that the testability is low after the completion of the logic design, the logic design needs to be restarted from the beginning,
In reality, it is a problem that testability is sacrificed.

SUMMARY OF THE INVENTION An object of the present invention is to generate a test pattern at high speed by performing propagation to an external output and setting an external input at a macro element level such as a counter, and to enable determination of testability while advancing logic design. And

[Means to solve the problem]

 FIG. 1 shows a principle configuration diagram of the present invention.

In FIG. 1, the symbol value assignment unit 3 selects a macro element to be tested from a logic circuit by focusing on a data path,
A symbol value (temporary symbol value) at the input of the macro element is assigned, and an output value corresponding to the symbol value is assigned by focusing on the function.

The propagation / setting processing unit 4 is for setting the external input to propagate the influence of the fault to the external output and to adjust the conditions with respect to these assigned symbol values.

The pattern embodying unit 5 generates a test pattern by substituting a specific constant value pattern for the assigned symbol value.

[Action]

In the present invention, as shown in FIG. 1, a symbol value assigning unit 3 selects a macro element to be tested from a logic circuit by focusing on a data path, assigns a symbol value to an input of the macro element, and has a function. Focusing on the output value corresponding to this symbol value, the propagation / setting processing unit 4 sets the external input to propagate the influence of the fault to the external output and adjusts the condition for the assigned symbol value, and embodies the pattern. The processing unit 5 substitutes a specific constant value pattern for these assigned symbol values to generate a test pattern.

Therefore, one symbol value is assigned to the input (multiple bits, for example, 16 bits) of the macro element to be tested, and the propagation / setting operation is performed. By generating test patterns by substituting the
At the stage of logic design, it is possible to determine testability and incorporate it.

〔Example〕

 First, the overall flow will be described with reference to FIG.

In FIG. 1, scheme design 1 describes a data path section and a control section corresponding to specifications. The data bus unit is obtained by connecting predefined macro element blocks by paths.

The logical design 2 is to design a function designed by the system design 1 to operate correctly. At this time, 3 to 5 also generate a test pattern at the macro element level according to the present invention.

The mounting design 6 is a design incorporated into an actual LSI or the like.

 Manufacturing 7 is to manufacture an LSI or the like.

Test 8 is to test the product using the test patterns generated by 3 to 5.

Shipment 9 is to ship LSIs that have passed the test to the customer.

Next, the configuration and operation of one embodiment of the present invention will be described with reference to the specific example of FIG. 3 in the order of the processing contents in FIG.

In FIG. 2, a symbol value allocating unit 3 performs processing and processing.

The process assigns symbol values to inputs. This is because, from the specifications designed by the system design 1 stored in the circuit diagram 11, the macro path to be used for test pattern generation is selected by focusing on the data path section, and the symbol value is input to the macro element. Means to assign.
For example, the symbol value P is assigned to the input of "R2 (register)" which is a macro element to be tested in the logic circuit in FIG.

In the processing, the macro element library 12 is searched, and a function that can be taken by the target element is selected from the functions, and then the output value of the macro element is given in the form of a symbol value function according to the function. For example, “P + 1” is given as an output value of the macro element “R2” to be tested, corresponding to “count up” which is one function of the macro element “R2” to be tested.

The propagation / setting processing unit 4 propagates the symbol value of the output of the macro element to be tested allocated in the processing in the data path unit to the external output, and gives the symbol value of the input of the macro element to be tested allocated in the processing. This is for setting external input. The propagation and setting results are described in the test description library 14. For example, in FIG. 3A, the symbol value “P + 1” is set to the external output C and the symbol value “P” is set to the external input B.

The pattern embodying unit 5 performs processing and processing.

In the processing, a binary value pattern is substituted for a symbol value.
This is a circuit synthesis process that creates a gate circuit from the specifications.
This means that a binary value pattern required for a function test is read from one item of 13 and substituted into a symbol value. still,
The binary value pattern may be obtained only inside the macro element.

The processing expands the external input value. This is the propagation
Since the logical values of the external output and the external input of the circuit are given as symbol values by the setting processing unit 4, the final test pattern is generated by substituting the binary value pattern read out in the processing into the symbol values. Means For example, a binary value pattern is substituted for the symbol "P" as the symbol value "P + 1" in the external output C generated by paying attention to the count-up function of the macro element "R" in FIG. This means that a final test pattern as shown in FIG. Similarly, an external input B (in this case, "P" which is the same as the input of the macro element "R2") is generated (the details will be described later with reference to FIG. 3).

As described above, the macro element to be tested is selected from the logic circuit, a symbol value is assigned to the input of the macro element, and the output value corresponding to the symbol value is output to the output by focusing on the function of the macro element. After the application, the propagation to the external output and the setting of the external input are performed, and at the finalized concrete stage, the binary value pattern is substituted into the function of the symbol value obtained for the external input and the external output to generate a test pattern. As a result, a test pattern can be generated at a high speed at a macro element level.
It is possible to generate a test pattern at a macro element level at a high speed, and at the same time, it is possible to perform a test facilitation design at the stage of logic design focusing on functions.

Next, the procedure for generating a test pattern for the macro element "R2" to be tested in the logic circuit of FIG. 3A will be specifically described with reference to FIGS.

First, the macro element "R2" to be tested in the logic circuit
Assign the symbolic value "P" to the input of.

Second, paying attention to "count up" which is a function of the macro element "R2", "P + 1" is assigned to the output.
This is because the macro element “R2” in FIG.
As shown in FIG. 4, the functions of load, clear, and count up are provided. Here, paying attention to the count up function, the symbol value "P + 1" obtained by counting up the input symbol value "P" as shown in FIG. "(Carry the symbol value" P ").

Third, for the macro element "R2", the external output C
As shown in FIG. 3 (a), the symbol value "P + 1" is calculated. This is because the symbol value “P + 1” of the output of the macro element “R2” to be tested is input to the macro element “A1 (adder)”, and “P” obtained by adding the other symbol “0” (zero) input.
+1 "is propagated to the external output C.
At this time, the macro element “R1” is set to be cleared so that “0” is input to the macro element “A1”.

Fourth, FIG. 3 (a) When the contents of each macro element constituting the logic circuit are determined, a binary value pattern is substituted for the symbol value "P" of the macro element "R2" to be tested. Generate test patterns. For example, as a test pattern for the symbol value "P" of the macro element "R2", a total of 17 test patterns as shown in FIG. Here, the input of the macro element “R2”,
The output, external input B, and external output C are all 16 bits.

FIG. 4 shows an example of a counter. This is because when the counter is only "load" as a function, the input value "D"
The output value "D" is sent to. On the other hand, when the counter is “load, count up” as the function, the input value “D”
Sends out the output value "D + 1". FIG. 3 (a) The macro element "R2" is the latter.

FIG. 5 shows an example of ALU (binary addition). This is a case where the ALU is a test target in FIG. 5A, and when the function is “binary addition”, test patterns are generated for a total of four sets of binary value patterns as shown in the figure. To do.

〔The invention's effect〕

As described above, according to the present invention, one symbol value is assigned to an input (a plurality of bits, for example, 16 bits) of a macro element to be tested, and then a propagation / setting operation is performed. When a test is completed, a specific constant value pattern is substituted to generate a test pattern, so that multiple bits can be
The setting operation can be performed at high speed, and at the stage of logic design, the testability can be determined by focusing on the function, and this can be adopted. As a result, a test pattern can be generated at high speed, and the efficiency of testability design can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is an explanatory diagram of a specific example of the present invention, FIG. 4 is a counter example, FIG. FIG. 6 is an explanatory view of the prior art. In the figure, reference numeral 3 denotes a symbol value assigning unit, 4 denotes a propagation / setting processing unit, and 5 denotes a pattern embodying process.

Claims (1)

(57) [Claims] In a test pattern generating apparatus for generating a test pattern of a logic circuit, a macro element to be tested is selected from the logic circuit by paying attention to a data path, a symbol value is assigned to an input of the macro element, and A symbol value allocating unit (3) for allocating an output value of this symbol value to an output paying attention to the function of the macro element
And a propagation / setting processing unit (4) for propagating the input and output symbol values to the external output and setting the external input at the macro element level. A pattern materialization processing unit (5) for generating a test pattern by substituting the materialized pattern for the set symbol value; and using the test pattern generated by the pattern materialization processing unit (5). A logic circuit test pattern generation device configured to perform a test of a logic circuit by using the test pattern generator.