JPH0294100A - Memory ic testing device - Google Patents
Memory ic testing deviceInfo
- Publication number
- JPH0294100A JPH0294100A JP63244076A JP24407688A JPH0294100A JP H0294100 A JPH0294100 A JP H0294100A JP 63244076 A JP63244076 A JP 63244076A JP 24407688 A JP24407688 A JP 24407688A JP H0294100 A JPH0294100 A JP H0294100A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- address
- test
- polarity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 38
- 230000015654 memory Effects 0.000 title claims abstract description 29
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体メモリ試験用パターン発生方法に係わり
、特に、３次元メモリの試験を行なうに好適なメモリＩ
Ｃ試験装置の構成に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor memory test pattern generation method, and in particular to a memory I suitable for testing three-dimensional memories.
C. Regarding the configuration of the test device.
従来の装置は、ｒＩＣテスタのメモリ・テスト機能を見
る」日経エレクトロニクス（１９７８，１０，１６）Ｐ
Ｐ６６−８２に見るように、１つのメモリテストパター
ン発生器からのアドレス出力に対し論理演算を施してデ
ータ変換を行なう。２つ以上のメモリテストパターン発
生器からのアドレス比較については何等考慮されておら
ず３次元構造を有するメモリにおいて、層間のデイスタ
ーブ試験を行なうことは配慮されていなかった。Conventional Equipment Sees Memory Testing Function of rIC Tester” Nikkei Electronics (1978, 10, 16) P.
As shown in pages 66-82, logical operations are performed on the address output from one memory test pattern generator to perform data conversion. No consideration has been given to comparing addresses from two or more memory test pattern generators, and no consideration has been given to performing a disturb test between layers in a memory having a three-dimensional structure.
上記従来技術は、メモリの読書き動作に対する各層間で
の互いの影響を調べるに必要なデータ発生の点について
配慮がされておらず、３次元メモリ特有の試験が不十分
となる問題があった。The above-mentioned conventional technology does not take into account the generation of data necessary to examine the mutual influence of each layer on memory read/write operations, and has the problem of insufficient tests specific to three-dimensional memory. .
本発明の目的はこれら上記の問題を解決する試験装置を
提供するにある。An object of the present invention is to provide a test device that solves the above-mentioned problems.
（課題を解決するための手段）
上記目的は、複数のメモリパターン発生器のアドレス出
力部分に、互いのアドレスが完全に一致したが、或は、
どちらか一方のアドレスが予め設定した他方のアドレス
のある範囲内に入っているか否かを比較する手段を設け
、その結果にもとづいてアクセスするデータの極性を制
御する手段を設けることにより達成される。(Means for Solving the Problems) The above object is to have address output portions of a plurality of memory pattern generators have addresses that completely match each other, or
This is achieved by providing means for comparing whether or not one address is within a preset range of the other address, and providing means for controlling the polarity of the data to be accessed based on the result. .
（作用）
上記、アドレスの比較手段やデータの極性を変換する手
段は試験装置全体を制御するＣＰＵにより予め動作内容
が決定されるか、或は、パターン発生器自身のプログラ
ムに従ってそれらの動作内容が決定される。(Function) The operations of the address comparison means and the data polarity converting means described above are determined in advance by the CPU that controls the entire test apparatus, or their operation contents are determined according to the pattern generator's own program. It is determined.
アドレスの比較手段は、今、試験着目している層のｘｉ
、ｙｉアドレスのテストセルに対し、他のデイスター
ブ用試験層ｊ層のｘｊ 、ｙｊが物理的なセル位置とし
てｘｊ ＝ｘｉ 、 ｙｊ ＝ｙＸＪ−△Ｘ≦ＸＪ≦×
１＋△Ｘ、ｙｌ−△ｙ≦ｙｊ≦ｙｉ十△ｙの全てか或は
一部を満足したか否かを比較し、その結果をデータ変換
信号としてデータの極性変換手段に送る。このとき、△
×、△ｙは、各々、Ｘアドレス、ｙアドレス方向での比
較判定範囲を示す。The means of comparing addresses is the xi of the layer we are currently focusing on in the test.
, yi address, xj and yj of other disturb test layer j are the physical cell positions, xj = xi, yj = yXJ-△X≦XJ≦×
It is compared whether all or part of 1+ΔX, yl-Δy≦yj≦yi+Δy is satisfied, and the result is sent to the data polarity conversion means as a data conversion signal. At this time, △
× and Δy indicate comparison determination ranges in the X address and y address directions, respectively.
データの極性変換手段は、上記アドレス変換手段からの
データ変換信号により（ｘｊ 、 ｙｊ ）のデータを
（ｘｉ 、 ｙｉ ）のデータを極性反転したものにし
たり、或は同極性にしたり等、１層とｊ層のデータ側の
論理演算を行なって層間デイスターブ試験を行う。The data polarity conversion means converts the data of (xj, yj) into the data of (xi, yi) by inverting the polarity or making it the same polarity by the data conversion signal from the address conversion means. A logical operation is performed on the data side of the j layer to perform an interlayer disturb test.
以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
図はメモリテストパターン発生器２台から成るメモリＩ
Ｃ試験装置の主要部構成である。The figure shows memory I consisting of two memory test pattern generators.
This is the main configuration of the C test device.
メモリパターン発生器（以下、ＭＰＧと略す）３．４は
タイミング信号発生器２からの動作基本クロック信号９
を入力し、メモリＩＣを試験するためのアドレス１１．
１２、データ１３．１４や各種の制御信号（制御信号は
図示していない）を出力する。A memory pattern generator (hereinafter abbreviated as MPG) 3.4 receives the basic operating clock signal 9 from the timing signal generator 2.
Enter address 11. to test the memory IC.
12, data 13.14 and various control signals (control signals not shown) are output.
本発明の要点であるアドレス比較回路５は上記ＭＰＧＩ
、ＭＰＧ２のアドレス出力１１．１２を入力し、予めＣ
ＰＵ１により設定した比較領域にもとづき互いのアドレ
ス関係を判定し、その結果をデータ変換信号１０として
データ変換回路６．７に出力する。データ変換回路６．
７では３次元メモリの各層間のデイスターブ試験を行な
うに必要な、上記アドレス比較回路５により、与えられ
たアドレス領域内でのデータ極性の制御を行なう。この
制御モードも予めＣＰＵＩからの計算機制御信号信＠８
によりテス］〜実行前に与えられる。データ変換回路６
．７ではデイスターブ層に相当する側のデータ極性をテ
スト着目層に与えられたデータの極性と反対になるよう
にしたり、同極性、或はＡＮＤ 、ＯＲ，ＥＸＯＲなど
の論理演算結果にし、層間デイスターブの試験が行なえ
るようになっている。The address comparison circuit 5, which is the main point of the present invention, is based on the above-mentioned MPGI.
, input address output 11.12 of MPG2, and set C in advance.
The mutual address relationship is determined based on the comparison area set by the PU 1, and the result is outputted as a data conversion signal 10 to the data conversion circuit 6.7. Data conversion circuit 6.
In step 7, data polarity within a given address area is controlled by the address comparison circuit 5, which is necessary for performing a disturb test between each layer of the three-dimensional memory. This control mode also receives a computer control signal from the CPUI in advance @8.
given before execution. Data conversion circuit 6
．． In 7, the data polarity on the side corresponding to the disturb layer is set to be opposite to the polarity of the data given to the test target layer, or the polarity is set to the same polarity, or the result of logical operations such as AND, OR, EXOR, etc., and the interlayer disturb is The test is now available.
なお、メモリテストパターン発生器は２台以上の複数台
を用意することも可能であり、それぞれのアドレス出力
の比較回路は本実施例をもとに容易に実現は可能である
。Note that it is also possible to prepare two or more memory test pattern generators, and a comparison circuit for each address output can be easily realized based on this embodiment.
又、データ変換回路６．７では、データの極性ばかりで
なく、２ビット以上で構成されたデータとしての変換の
役割りも与えることが可能である。Further, the data conversion circuit 6.7 can not only change the polarity of data but also convert the data into data composed of two or more bits.
これにより、マルチＩ１０構成のデータを有するメモリ
に対してもより効果的な試験が可能となる。This enables more effective testing even for memories having data in a multi-I10 configuration.
本発明によれば、従来構成のメモリＩＣ試験装置では不
可能であった３次元メリの層間デイスタブを試験できる
効果がある。According to the present invention, it is possible to test three-dimensional interlayer distubs, which was impossible with a memory IC tester having a conventional configuration.
層間デイスターブ試験を行なうにあたり、各層ごとのテ
ストパターンを独立に発生することが可能であり、その
際、層間デイスターブのためのデータ極性について何等
プログラム上の考慮が不要となり、試験実行が容易とな
る。When performing an interlayer disturb test, it is possible to generate a test pattern for each layer independently, and in this case, there is no need to take into account any programming considerations regarding data polarity for interlayer disturb, making test execution easier.
メモリテストパターン発生器を２台以上設（プることに
より、層間デイスターブの試験効率を一層上げるととも
に、３次元メモリＩＣの試験時間が短縮可能となる。By installing two or more memory test pattern generators, it is possible to further improve the interlayer disturb test efficiency and shorten the test time for three-dimensional memory ICs.
図は本発明の一実施例を示すブロック図である。
１・・・ＣＰＵ、２・・・タイミング信号発生器、３．
４・・・メモリテストパターン発生器、５・・・アドレ
ス比較回路、６．７・・・データ変換回路、８・・・計
算機制御信号、１０・・・データ変換信号、１５・・・
データ出力。
手
続
補
正
書
（方式）
％式％
補正をする者
４Ｌ件との関係The figure is a block diagram showing one embodiment of the present invention. 1... CPU, 2... Timing signal generator, 3.
4...Memory test pattern generator, 5...Address comparison circuit, 6.7...Data conversion circuit, 8...Computer control signal, 10...Data conversion signal, 15...
Data output. Procedural amendment (method) % formula % Person making the amendment Relationship with 4L matters
Claims (1)
アドレス出力を入力し、互いのアドレス関係を比較する
アドレス比較手段と、その結果にもとづき被試験メモリ
に与えるデータを変換する変換手段を設けたこと特徴と
するメモリＩＣ試験装置。1. A plurality of memory test pattern generation means, an address comparison means for inputting these address outputs and comparing the mutual address relationships, and a conversion means for converting the data given to the memory under test based on the results. Features of memory IC testing equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63244076A JPH0294100A (en) | 1988-09-30 | 1988-09-30 | Memory ic testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63244076A JPH0294100A (en) | 1988-09-30 | 1988-09-30 | Memory ic testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0294100A true JPH0294100A (en) | 1990-04-04 |
Family
ID=17113377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63244076A Pending JPH0294100A (en) | 1988-09-30 | 1988-09-30 | Memory ic testing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0294100A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483488A (en) * | 1993-09-24 | 1996-01-09 | Nec Corporation | Semiconductor static random access memory device capable of simultaneously carrying disturb test in a plurality of memory cell blocks |
| KR100348760B1 (en) * | 1998-11-19 | 2002-08-13 | 삼성전자 주식회사 | semiconductor memory test method and apparatus thereof |
-
1988
- 1988-09-30 JP JP63244076A patent/JPH0294100A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483488A (en) * | 1993-09-24 | 1996-01-09 | Nec Corporation | Semiconductor static random access memory device capable of simultaneously carrying disturb test in a plurality of memory cell blocks |
| KR100348760B1 (en) * | 1998-11-19 | 2002-08-13 | 삼성전자 주식회사 | semiconductor memory test method and apparatus thereof |
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