JPH0413679Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a 24-hour alarm clock that issues an alarm sound at a set time once every 24 hours.

(Prior Art) Attempts have been made to improve conventional clocks that issue an alarm sound at a set time once every 12 hours to clocks that issue an alarm sound at a set time once every 24 hours. This is because an alarm is normally used once a day (24 hours); an example is Japanese Patent Application Laid-open No. 55-39018. This configuration has an added circuit that converts the 12-hour cycle ON signal from the standard into a 24-hour cycle ON signal, allowing you to use a normal 12-hour movement to convert it into a 24-hour alarm clock. There are advantages.

(Problem that the invention aims to solve) However, with these 24-hour alarms, the alarm is generally set at night to the next day's wake-up time, and in such cases, the alarm is set within 12 hours. Therefore, when the alarm set switch is set, an alarm is output with the next reference signal, and the alarm is sounded again 24 hours after the same time. Therefore, when using a 12-hour alarm, if you want it to sound 24 hours later, it is necessary to set the time set for the 12-hour alarm again as a 24-hour alarm, which makes the switch operation more complicated and requires a large number of components. The problem was that it was necessary.

(Means for solving the problem) The present invention provides a display circuit that displays the count status of a binary counter that converts a 12-hour cycle ON signal into a 24-hour cycle ON signal. In addition to making it possible to clearly identify whether the alarm sound will be sounded at the time that coincides with the time or 12 hours later, the next guide signal will be passed when the alarm output is stopped using the stop switch. 12 hours and 24 hours alarm
This simplifies the operation of setting a 24-hour alarm.

(Embodiment) The drawing is a circuit diagram of a 24-hour alarm clock according to an embodiment of the present invention.

The oscillation circuit 2 generates a time reference signal, and the frequency of this reference signal is divided by the frequency dividing circuit 4 to a desired frequency, for example, 1 Hz. This frequency signal is converted into a pulse signal with a desired pulse width by a waveform shaping circuit 6, and this pulse is amplified by a drive circuit 8 and supplied to a motor 10. motor 10
rotates in response to this pulse, driving the wheel train and hands to display the time.

The reference switch 12 is incorporated into a clock wheel train that rotates once every 12 hours, and is configured to be turned on when a set time arrives. This guideline switch 12
The signal is inputted via an inverter 14 and a chattering prevention circuit 16 to a reference signal control circuit 24 consisting of FFs 18 and 20 and an OR gate 22. This guideline switch 12, inverter 14
and the chattering prevention circuit 16 constitute a reference circuit 26.

On the other hand, the output signal from the chattering prevention circuit 16 is input to the clock input φ of the FF 18 constituting the binary counter 24, and the Q output signal of the FF 18 is input to the clock input φ of the FF 20. The output signal of the OR gate 28 is input to the reset input R of both FFs 18 and 20, and the output signal of the AND gate 30 and the counter 31 that counts the constant periodic signal from the frequency dividing circuit 4 is input to the OR gate 28. are doing. Furthermore, and gate 3
0, a signal from the switch 34 for stopping notification via the inverter 32 and the Q output signal of the FF 20 are input. Further, the output signal of the OR gate 22 is input to the reset input R of the FF 20. This OR gate 22 includes the output signal of the OR gate 28 and a one-shot multivibrator 36,
An operation signal from an alarm set switch 40 via an inverter 38 is input. This signal is also input to the set input S of the FF18.

This becomes the output signal of the reference signal control circuit 24. The output signal of the FF 18 is input to the reset input R of the counter 31. The Q output signal is also input to an AND gate 42. This and gate 42
, the output signal of the inverter 38 and the frequency dividing circuit 4
AND gate 4 whose input signal is the signal in the middle of
A gate circuit 4 for creating a notification signal consisting of 4
6 output signals are input. The output signal of the AND gate 42 is input to the driving transistor 52 of the speaker 50 via the inverter 48. The AND gate 42, the inverter 48, the speaker 50, and the driving transistor 52 constitute a notification circuit 54.

The present invention includes a display circuit 56 that displays whether the alarm will be reported at the next time the reference switch 12 is turned on or the second time the reference switch 12 is turned on. This display circuit 56 includes an AND gate 62 to which an output signal from an OR gate 60 and a Q output signal of the FF 18 are input, which constitutes a blinking signal forming circuit 58 for forming a blinking signal using a pulse output signal from the waveform shaping circuit 6; It has an inverter 64 and a capacitor 66 connected in series to the output terminal of the AND gate 62, as well as an LED 68 and a diode 70 connected in series. One end of this capacitor 66 is connected to both the LED 68 and the diode 70.

The operation of this circuit will be explained below.

First, when the alarm set switch 40 is turned on, the output signal of the inverter 38 becomes H level, and at the same time, the one shot multivibrator 36 generates a positive single pulse. This pulse causes the Q output signal of FF 18 to go to H level, and the Q output signal of FF 20 to go to L level and H level, respectively. As a result, the counter 31 is reset.

After this, the set time arrives and the guide switch 12 is turned on.
When turned on, the output signal of the inverter 14 rises to H level. This rising signal causes FF
The Q output signal of FF 20 is inverted and falls to L level, and this falling signal inverts the Q output signal of FF 20 to H level and the output signal to L level. This FF20 Q output H level signal,
The AND gate 42 is opened by the H level signal from the inverter 38, the notification signal from the gate circuit 46 is input to the driving transistor 52, and the speaker 50 generates notification sound.

At this time, when the user turns on the alarm stop switch 34, the output signal of the inverter 32 goes high.
rise to the level. This H level rising signal is passed through the AND gate 30, which is in an open state due to the Q output signal of the FF 20, and the OR gate 28 to the FF.
Input to reset input R of 18 and 20, both FF1
8, 20. With this, FF20
The Q output signal of becomes L level, and AND gate 4
2 closes and the notification sound stops.

Even without turning on the notification stop switch 34, the counter 31 is reset and starts counting when the output signal of the FF 20 becomes L level, and the carry output signal after a certain period of time also causes the FF 18, 20 is reset, so the notification sound stops.

In this manner, when the alarm set switch 40 is turned on, a notification sound is generated at the next time when the reference switch 12 is turned on. This is because when the user turns on the alarm switch 40, it is often necessary to generate a notification sound at the next time when the reference switch 12 is turned on.

However, when the reference switch 12 is turned on again after 12 hours have passed and the output signal of the inverter 14 rises, the Q output signal of the FF 18 is only inverted to H level and no notification sound is generated. After another 12 hours, the reference switch 12 is turned on again, the Q output signal of the FF 18 falls to the L level, the Q output signal of the FF 20 goes to the H level, and the output is inverted to the L level. As a result, a notification sound is generated from the notification circuit 54, and when this notification sound is stopped, both the Q output signals of the FFs 18 and 20 return to the L level. Therefore, even after this, the indicator switch 12 is turned on twice, that is, the notification sound is generated only every 24 hours.

Here, when the Q output signal of FF18 is at H level, the AND gate 62 in the display circuit 56 opens,
The blinking signal from the OR gate 60 is sent to the inverter 64.
will be supplied to When this blinking signal is at L level, current flows from the inverter 64 side through the capacitor 66 and the diode 70, and the capacitor 66 is charged. And the blinking signal is H
When the level is reached, current flows to the LED 68, capacitor 66, and inverter 64, and the LED 6
8 lights up. In this way, the LED 68 repeatedly turns on and off in response to changes in the level of the blinking signal.

However, when the Q output signal of the FF 18 is at the L level, the AND gate 62 is closed and the output signal of the inverter 64 remains at the H level.
LED58 does not light up.

In this way, the Q output signal of FF18 is at H level,
In other words, when the next time the indicator switch 12 is turned on and a notification sound is generated, the LED 68 of the display circuit 56
blinks, and the LED 68 is off when the Q output signal of the FF 18 is at L level, that is, when the notification sound is not generated unless the reference switch 12 is turned on twice.

(Effect of the invention) As described above, according to the invention, depending on the display state of the display circuit, the user can decide whether to notify by turning on the guide switch next time or by turning on the guide switch 12 hours later. This makes it possible to prevent erroneous settings in which the notification sound is not generated at a required time or, conversely, is generated at an unnecessary time. Furthermore, by providing a stop switch, it is possible to automatically set the next alarm 24 hours later by stopping the alarm using the stop switch, thereby simplifying the setting operation.
In addition, when the next day's alarm is not required, just like a normal alarm clock, you can turn it off using the alarm set switch, and the operation for using it every 12 hours is the same as before, so it is easy to operate.

[Brief explanation of the drawing]

The drawing is a circuit diagram of a 24-hour alarm clock according to an embodiment of the present invention. 24... Reference signal control circuit, 26... Reference circuit, 54... Notification circuit, 56... Display circuit.

Claims (1)

[Scope of claim for utility model registration] In a 12-hour alarm clock that outputs an alarm signal at a preset time every 12 hours, the clock counts signals from a reference circuit that outputs a reference signal at preset times, and The count value is set to 1 by setting the alarm set switch that instructs the output of an alarm at a preset time.
a reference signal control circuit that outputs a control signal in response to a falling signal from a binary counter set to , a notification circuit that outputs an alarm in response to the control signal and the alarm set switch, and an alarm circuit that outputs the alarm. A stop switch that clears the binary counter and stops outputting the control signal when operated at a certain time.