JPH0443834Y2 - - Google Patents

Description

[Detailed explanation of the idea] (Industrial application field) The present invention relates to an alarm clock.

(Prior art) As shown in Japanese Patent Application Laid-Open No. 61-213788,
A technique for controlling an alarm sound according to the length of sleep time has been disclosed. This means that when you sleep for a long time and are in a light sleep, for example, you can lower the alarm volume to wake you up refreshed, and when you sleep for a short time and are in deep sleep, you can increase the alarm volume to ensure that you wake up. can.

(The problem that the invention aims to solve) However, the depth of sleep, or in other words, the difficulty of waking up, may not be determined solely by the amount of sleep that day.

For example, if you slept extremely short the previous day, such as by staying up all night the night before, even if you sleep normally the next night, your sleep will be deeper than usual, and there is a risk that you will not be able to wake up with the alarm sound controlled by the conventional mechanism. The sex was hot.

(Means for solving the problem) For this purpose, the present invention provides two counters that count sleep time, causes these counters to count the sleep time of the previous day and the current day, and adds up these two sleep times. An adder circuit is provided to increase the alarm volume when the added value is less than a certain value. In order to cause the two counters to alternately count the sleeping time, a count switching circuit is provided which inverts the output state each time the alarm is set and switches the counts of the two counters based on the output signal. It is characterized by

(Embodiment) The drawing is a circuit diagram according to an embodiment of the present invention.
The reference signal generator 2 consists of an oscillator 4 and a frequency divider 6, and from the middle of this frequency division stage, constant period signals φ ₁ ,
Notification signal φ ₂ is output. Further, the time display circuit 8 for displaying the time includes a waveform shaping circuit 10.
Consists of a driver 12, motor 14, and wheel train 16,
This has the same configuration as a normal hand-type analog display watch. The indicator 18 is incorporated into the wheel train 16 and serves as an alarm detection circuit that outputs an alarm-on signal (H level) at the same time as the set time arrives. This alarm-on signal is input to the AND gate 22 into which the aforementioned notification signal φ ₂ and the signal from the alarm set switch 20 are input. Therefore, the AND gate 22 outputs the notification signal φ ₂ in synchronization with the generation of the alarm-on signal when the alarm set switch 20 is in the set (on) state. The signal from the AND gate 22 is input to the sound generation circuit 26 via the alarm volume control circuit 24 to generate a notification sound. The alarm volume control circuit 24 includes a resistor 28 and a transistor 30 connected in parallel with the resistor 28.
When the transistor 30 is turned on, this resistor 28 is bypassed, so a large current flows through the sound generation circuit 26, increasing the volume. Conversely, when the transistor 30 is turned off, the resistor 28 is bypassed.
Current will flow through 8, and the volume will become lower.

The output signal of the comparator circuit 32 is input to the gate input of this transistor 30. This comparison circuit 32 includes a sleep time memory circuit 34 in which a predetermined sleep time is stored, and a sleep time memory circuit 34 that adds up the time from when the alarm set switch 20 is set to when it is not set for the previous day and the current day. The value is compared with the sleep time counter 36 which outputs the value, and if the value of the sleep time counter 36 is small, the transistor 3
A signal that turns on 0 is output, and if the signal is large, the transistor 30 remains off.

In this embodiment, the sleep time memory circuit 34 is configured so that when the average sleep time per day is input, the value is automatically doubled. , a counter 42 for counting the number of operations of the input switch 38, and a shift register 44 for presetting the count value of the counter 42. Furthermore, there is an AND gate 46 between the input switch 38 and the clock input φ of the counter 42, which is controlled to open and close by the lock switch 40, and the reset input R of the counter 42 receives a single pulse when the lock switch 40 is closed. A one-shot multivibrator 48 that generates is connected. For this purpose, the count value of the counter 42 is cleared at the same time as the lock switch 40 is closed, and the AND gate 46 is opened and the input switch 38 is closed.
It is now possible to input sleep time by operating .

Further, an inverter 50 and a one-shot multivibrator 52 are connected to the lock switch 40.
2, a single pulse is generated by opening a lock switch 40. This single pulse is directly input to the PE input of the shift register 44,
A delay circuit 54 is input to the clock input φ. Therefore, the count value of the counter 42 is preset in the shift register 44 at the same time as the lock switch 40 is opened after the input operation by the input switch 38 is completed, and then shifted to the upper bit by one bit by the pulse input to the clock input φ. This shift doubles the value preset in the shift register 44. This means that the shift register 44 stores two days worth of average sleep time. And this shift register 4
The count value of 4 is input to the comparison circuit 32.

On the other hand, the sleep time counter 36
counters 56, 58, count switching circuit 60,
It consists of an adder circuit 62. Count switching circuit 60
are a one-shot multivibrator 64 that generates a single pulse when the alarm set switch 20 is set, an FF 66 that inverts the signal of the output Q every time this single pulse is generated, and the Q,
The one-shot multivibrators 68 and 70 each generate a single pulse each time the Q output rises to the H level, the alarm set switch 20 and the constant period signal _φ1 are input together, and the Q output and output of the FF66 are input to the other input. are entered respectively,
The output signal is transmitted to the first and second counters 56, 58
and AND gates 72 and 74 input to the .

Therefore, each time the alarm set switch is set, the Q output of the FF 66 is inverted, the count value of either the first or second counter 56, 58 is cleared, and the count value of either the AND gate 72, 74 is cleared. Open it and start counting. This continues until the alarm set switch 20 is unset. As a result, the counter counts the number of sleeping hours per day from when the alarm is set until it is unset.
Then, when you set the alarm again the next day, FF
The output of 66 is inverted, and the counter that was not counting now counts, and the count value of the other counter is held as is.
Therefore, the count value inputted to the addition circuit 62 is always the sleep time of the previous day and the current day, and the addition circuit 62 inputs the value obtained by adding these times to the comparison circuit 32.

As a result, the comparison circuit 32 compares a value twice the preset average sleeping time with the sum of the actual sleeping hours of the previous day and the current day, and if the actual sleeping time is shorter, a signal is sent to turn on the transistor 30. output and increase the alarm volume.

(Effects of the invention) As described above, according to the invention, since the volume of the alarm sound is controlled taking into account the amount of sleep the previous day, the alarm sound is adjusted to suit the physical condition of the user, which cannot be determined by just the amount of sleep that day. can occur, allowing you to wake up more reliably and refreshed.

[Brief explanation of drawings]

The drawing is a circuit diagram of an alarm clock according to an embodiment of the present invention. 2... Reference signal generator, 8... Time display circuit,
20...Alarm set switch, 24...Alarm volume control circuit, 34...Sleep time memory circuit,
36...Sleep time counter.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator that generates a reference signal, a time display circuit that receives this reference signal and displays the time,
An alarm detection circuit that detects when the time displayed by the time display circuit has reached the set time, and an alarm set switch, and a notification signal only when the alarm set switch is in the set state and a detection signal is generated from the alarm detection circuit. an AND circuit that outputs a notification sound, a sound generation circuit that receives a notification signal from the AND circuit and generates a notification sound, a sleep time memory circuit that stores a preset sleep time, and an alarm set switch that is in a set state. a sleep time counter that counts the reference signal only when
a comparison circuit that compares the count values of the sleep time memory circuit and the sleep time counter and outputs a comparison signal; and a volume that controls the volume of the notification sound produced by the sound generation circuit based on the comparison signal from the comparison circuit. An alarm clock having a control circuit, wherein the sleep time counter includes first and second clocks capable of counting the reference signal.
each time the alarm set switch is set, the output state of the counter is inverted, and in response to the output signal, only one of the first and second counters starts counting the reference signal from the beginning. An alarm clock comprising: a count switching circuit; and an addition circuit that adds the count values of the first and second counters.