JPH0216316Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to the improvement of a watch with a snooze function, and especially when the snooze operation time is extended.
The present invention relates to a device configured such that alarm notification does not stop unless the number of operations of the snooze switch is increased accordingly.

(b) Prior Art A conventional watch with a snooze function is disclosed in Japanese Patent Publication No. 61-24670. The snooze function of this watch is set so that alarm notification starts and when the snooze switch is operated once, alarm notification is temporarily stopped.

(c) Problems that the invention aims to solve Humans sleep at times when it is deep and at times when it is light. Therefore, when the user is in a deep sleep, if the notification sound is stopped by a simple operation such as operating a switch once, the problem arises that the user will not be able to wake up even after a long period of time. For this reason, it is necessary to complicate the operations, but when a person is in a light sleep, even a simple operation can wake him up, causing the problem that complicated operations become more bothersome.

(d) Means for Solving the Problems The purpose of the present invention is to provide a timepiece that can be used reliably and quickly, regardless of the depth of sleep of the user, and that does not require unnecessary operations.

To this end, the present invention changes the number of times the snooze switch is operated to stop the alarm notification depending on the depth of sleep of the user. That is, in the present invention, the depth of sleep of the user is
It is detected by the alarm notification time, and when the notification time is long, it is assumed that the person is in deep sleep, and the number of times the switch is operated to stop the alarm is increased, and when the notification time is short, it is assumed that the sleeper is light sleep, and the number of switch operations is decreased. I'm letting you do it.

(e) Examples Examples of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing a circuit configuration of a watch with a snooze function according to an embodiment of the present invention.

A reference signal generator 1 generates a reference signal, and is composed of an oscillator 2 and a frequency dividing circuit 6.

Reference numeral 4 denotes a time display mechanism that inputs a reference signal and displays the time, and in this embodiment, it has a configuration for an analog clock. That is, the reference signal generator 1
A waveform shaping circuit 8 that shapes the waveform of the reference signal from
, a drive circuit 10 that converts the output signal into a drive signal, and a motor 12 driven by the drive signal.
and a wheel train 14 that is driven by this motor 12 to move the pointer.

16 is a detection signal A at a preset time.
It is a reference circuit that outputs a contact switch 18 that is turned on by the operation of the wheel train 14 at the time set by the reference mechanism, and an AND gate that inputs its output signal to one input terminal and outputs a detection signal A. It consists of 20.

In the case of a digital clock, there is a matching system that outputs a detection signal when the output signals of the alarm time setting circuit, which allows you to arbitrarily set the time by operating an external operating member, and the clock circuit, which counts the current time, match. Consists of circuits.

22 is a ring stop switch, the output signal of which is applied to the other input terminal of the AND gate 20 in the reference circuit 16.

24 is a notification circuit that outputs a notification signal in response to the detection signal A from the reference circuit 16.

This notification circuit 24 is a one-shot multivibrator (hereinafter referred to as "OSM") which inputs the detection signal A from the reference circuit 16 and outputs a pulse in response to the detection signal A.
) 26 and the detection signal A to the inverter 3
0, and a flip-flop (hereinafter referred to as "OSM 28") which inputs output signals B and C of OSMs 26 and 28 to a set input S and a reset input R via OR gates 34 and 36, respectively. (abbreviated as “FF”) 32,
FF 38 that inputs signals B and C to set input S and reset input R, respectively, and AND gate 39 that inputs signals D and E from outputs Q of FF 32 and 38.
and an AND gate 40 which inputs the output signal G and the signal φ ₂ from an intermediate stage of the frequency dividing circuit 6 and outputs the notification signal M.

Reference numeral 42 denotes a sound generation circuit that generates an alarm notification sound in response to the notification signal M output from the notification circuit 24.

44 is a snooze switch, and by operating this snooze switch 44, alarm notification can be temporarily stopped.

46 is a snooze counter, and the notification circuit 24
When the notification signal M is being output from the snooze switch 44, a notification start signal H is outputted to start notification again after a certain period of time has been counted since the snooze switch 44 was turned on.

This snooze counter 46 receives the clock signal φ ₁ from an intermediate stage of the frequency dividing circuit 6, and starts counting when the reset is released, and outputs a notification start signal H when the count is increased.
Signal F from the output of FF 38 in the notification circuit 24
and an OR gate 50 which inputs an output signal J of a matching circuit to be described later and applies the output signal to a reset input R of a counter 48.

52 is a notification time counter that starts counting when alarm notification starts and counts the alarm notification time. This notification time counter 52 includes a counter 53 that inputs the clock signal φ ₁ to the clock input φ, and an AND gate 3 in the notification circuit 24.
9 and an inverter 51 which inverts the output signal G of the counter 9 and applies it to the reset input R of the counter 53.

Reference numeral 54 denotes an operation counter that counts the number of operations of the snooze switch 44 while the notification signal M is being outputted from the notification circuit 24. The counter 58 includes an AND gate 56 which inputs an output signal G, and a counter 58 which inputs the output signal to a clock input φ and inputs a signal L from an operation interval counter to be described later to a reset input R.

60 is an operation interval counter for detecting whether or not the snooze switch 44 has been operated within a predetermined time; , the clock signal _φ1 from the middle stage of the frequency divider circuit 6 is inputted to the clock input φ, and the FF6
The signal K from the output of 2 is input to the reset R, and the signal L is input to the counter 58 in the operation number counter 54.
The counter 66 is configured to apply a signal to the reset input R of the FF 62 and the reset input R of the FF 62.

68 is a counter 53 in the notification time counter 52
This is a coincidence circuit that compares the count value of the counter 58 in the operation number counter 54 and outputs a coincidence signal J.

Next, the operation of the snooze function watch according to this embodiment having the above configuration will be explained based on the time chart shown in FIG.

First, when the ring stop switch 22 is on and the AND gate 20 in the reference circuit 16 is open, when the set alarm time comes, the contact switch 18 is turned on and the output of the AND gate 20 is turned on. Signal A becomes H level.

When this detection signal A goes to H level, a pulse is output from the OSM 26 in the notification circuit 24 in response to its rising edge.

The pulse generated in this signal B is FF32,3
8 set inputs S to set them.

Therefore, each output signal D, E,
F becomes H, H, and L levels, respectively. Therefore,
AND gate 39 inputting signals D and E becomes open, and its output signal G also becomes H level. Therefore, the AND gate 40 is also opened, and the clock signal φ ₂ is generated at its output.

In this way, the notification signal M having the frequency component of the clock signal φ ₂ is applied to the sound generation circuit 42, and the sound generation circuit 42 generates an alarm notification sound.

Further, when the output signal G of the AND gate 39 rises to H level, it is inverted by the inverter 51 and inputted to the reset input R of the counter 53.
is reset and starts counting.

Assuming that the alarm notification continues and the count value of the counter 53 now reaches "2", the user, who was a light sleeper, will realize this and turn the snooze switch 4.
4 is operated twice, the pulse generated in the operation signal I is generated at the output of the AND gate 56 in the operation number counter 54, which is already in the open state.

Counter 58, which inputs this pulse to clock input φ, counts this pulse and sets its counter value to "2".

As a result, the matching circuit 68 detects the notification time counter 5.
2 and the count value of the operation number counter 54 are detected, and a pulse is generated in the output signal J.

When a pulse is generated in the match signal J, the FF 32 in the notification circuit 24 is reset to input this pulse to the reset input R via the OR gate 36, and its output signal D becomes L level. Therefore, the AND gates 39 and 40 are closed, the notification signal M is held at L level, and the generation of the alarm notification sound from the sound generation circuit 42 is temporarily stopped.

Further, since the AND gate 39 is closed, its output signal G becomes L level, and the counter 53 in the notification time counter 52, which inverts this signal and inputs it to the reset input, is reset.

On the other hand, the pulse generated in the match signal J is also applied to the reset input R of the counter 48 via the OR gate 50 in the snooze counter 46, so that the counter 48 shifts the register in response to the input clock signal _φ1 . Start.

The pulse generated at the output of the AND gate 56 in the operation number counter 54 when the snooze switch 44 is operated is the FF in the operation interval counter 60.
is applied to the set input S of 62 to set it.

Therefore, the output signal K of this FF 62 becomes L level, the counter 66 starts counting, and after counting for several seconds, outputs a pulse to its output signal L. The pulse generated in this signal L is applied to the reset input R of FF62 to reset it.
Furthermore, it is applied to the reset input R of the counter 58 in the operation number counter 54 to reset it and return it to its initial state.

Counter 4 in the snooze counter 46 described above
8 counts up for several minutes, its output signal H
A pulse is generated. The pulse generated in this signal H is passed through the OR gate 34 in the notification circuit 24.
It is applied to the set input S of FF32.

When this pulse is input, the FF 32 returns to the set state, and its output signal D becomes H level again.

Therefore, the AND gates 39 and 40 are opened, and the notification signal M having the frequency component of the clock signal φ ₂ is again applied to the sound generation circuit 42 to start alarm notification.

Further, when the AND gate 39 is opened and its output signal G becomes H level, the counter 53 in the notification time counter 52 starts counting again as described above.

This time, it is longer than the previous alarm notification and the count value of the counter 53 reaches "3".
The user who noticed this was snooze switch 44.
When is turned on three times, the three pulses generated in the operation signal I are applied to the clock input φ of the counter 58 via the AND gate 56 in the operation counter 54, setting the count value to "3". .

As a result, in the same manner as described above, the matching circuit 68 detects that the count values of the notification time counter 52 and the number of operation counters 54 match, and generates a pulse in the output signal J.
In response to the pulse generated in this signal J, the notification signal M is held at L level and the alarm notification is temporarily stopped.

As the notification time becomes longer in this way, the count value of the counter 53 in the notification time counter 52 advances rapidly, and the alarm notification cannot be stopped unless the snooze switch 44 is operated the same number of times as the count value.

Now, assuming that the snooze switch 44 is operated only once when the count value of the counter 53 in the alarm time counter 52 reaches "2" after a certain period of time has elapsed since the alarm notification was started again, AND gate 56 in number counter 54
Only one pulse will be generated at the output.

Therefore, the counter 58 counts these pulses and sets the count value to "1".

Therefore, the count values of the notification time counter 52 and the operation number counters 53 and 58 do not match, and no pulse is generated in the output signal J of the matching circuit 68. Therefore, as described above, the FF 62 in the operation interval counter 60, which is set when the snooze switch 44 is operated, remains set.

Therefore, after counting for several seconds, the counter 66
It counts up and generates a pulse in its output signal L.

The counter 58 in the operation counter 54 is reset by the pulse generated in the signal L.

During this time, the counter 5 in the notification time counter 52
3 continues to count, and when the count value reaches "4", the snooze switch 44 must be turned on four times to set the count value of the counter 58 in the operation number counter 54 to "4". Otherwise, alarm notification cannot be stopped. Moreover, when the snooze switch 44 is operated for the first time, the counter 66 in the operation interval counter 60
If the fourth operation is not completed between when the counter 60 starts counting and when a pulse is generated on the output signal L, the count value of the counter 58 is cleared.
Further alarm notifications will continue.

If the snooze switch 44 is operated four times within a predetermined period of time, a pulse is generated in the output signal J of the coincidence circuit 68 in the same manner as described above, and the alarm notification is temporarily stopped.

Incidentally, in order to completely stop the alarm notification, the ringing stop switch 22 may be turned off.

When the ring stop switch 22 is turned off, the AND gate 20 in the reference circuit 16 is closed, and its output signal A becomes L level.

The falling edge of the signal A is inverted by the inverter 30, and in response to the rising edge of the inverted signal A, the OSM 28 outputs a pulse.

The pulse generated in this signal C is FF32,3
8 reset inputs R to reset them.

As a result, signals D, E, and F are L, L, and L, respectively.
Goes to H level, AND gate 39, 40, 56
is closed, the counter 48 is maintained in a reset state, and alarm notification is stopped.

As mentioned above, in this embodiment, the alarm notification cannot be stopped unless the number of times the snooze switch is operated according to the alarm notification time, and the snooze switch must also be operated within a predetermined time. For example, the count of the number of times the snooze switch is operated is reset.

(f) Effect of the invention According to the invention, by making the operation of the snooze switch simple or complicated depending on the depth of the user's sleep, the user can be operated reliably, quickly, and with the least waste. I can wake up.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of a watch with a snooze function according to an embodiment of the present invention, and FIG. 2 is a time chart of FIG. 1. 1...Reference signal generator, 4...Time display mechanism,
16...Reference circuit, 22...Sound stop switch,
24...Notification circuit, 44...Snooze switch,
46... Snooze counter, 52... Notification time counter, 54... Operation number counter, 60... Operation interval counter, 68... Matching circuit.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator that generates a reference signal, a time display mechanism that displays the time using the reference signal from the reference signal generator, and a time displayed by the time display mechanism that is preset. a reference circuit that detects when the specified time has arrived; a notification circuit that outputs a notification signal in response to a detection signal from the standard circuit; and a sound generation circuit that generates a notification sound in response to the notification signal from the notification circuit. a snooze switch that stops outputting the notification signal to the notification circuit; and a snooze switch that enables the reference signal from the reference signal generator to be counted only while the notification signal is being output from the notification circuit; a snooze counter that outputs a notification start signal that causes the notification circuit to output a notification signal when the count value is cleared in response to the ON operation signal and the count value reaches a constant value; The watch includes: a notification time counter that counts the generation time of the notification signal from the notification circuit; an operation frequency counter that counts the number of times the snooze switch is operated while the notification signal is output from the notification circuit; Clearing starts counting the reference signal from the reference signal generator from the time when the operation number counter first starts counting, and clears the count value of the operation number counter when the count value exceeds a certain value. an operation interval counter that outputs a signal; a coincidence circuit that compares the count values of the notification time counter and the operation number counter and supplies a coincidence signal to the notification circuit in place of the snooze switch operation signal when they match; A watch with a snooze function.