JP2508441Y2 - Alarm clock with snooze - Google Patents

Description

[Detailed description of the device]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm clock with snooze, and more particularly to a device for changing the time display according to the operation of a snooze switch when an alarm occurs.

[0002]

2. Description of the Related Art A conventional alarm clock with snooze is designed to generate an alarm at a set time, and then operate the snooze switch to generate an alarm again after a certain period of time to give an alarm for the wake-up time. However, after the temporary stop operation, he fell asleep again and was late for the promised time. In order to prevent such a situation, there is provided an alarm clock in which the alarm volume is sequentially increased according to the number of snooze operations or the alarm generation time.

[0003]

However, all of the above-mentioned conventional methods are audible alarms, and when the wake-up is set so that there is enough time to wake up, which is an absolute condition for waking up, or the wake-up is faster than usual. I was overslept. The present invention focuses on such a point, and an object thereof is to prevent a person from oversleeping by visually giving a warning by changing the time display to allow a snooze operation to wait for another alarm.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention counts a reference signal and displays the time, generates an alarm at a set time, and operates a snooze switch for instructing an alarm suspension. , In the alarm clock with snooze that generates an alarm again after a certain period of time,
It is characterized in that a constant pulse number output circuit is provided for advancing the display time by a predetermined time according to the operation of the snooze switch when an alarm occurs.

[0005]

When the alarm sounds at the set time and the snooze switch is operated, the alarm sound is stopped and the stepping pulse for a fixed time is input to the timekeeping section. When the snooze pause period elapses and an alarm occurs again and the time is confirmed, the time display will be a display time that is a certain time ahead of the actual time,
When the snooze switch is operated again, the display time is advanced by a certain amount of time, and the time is multiplied by the number of times of operation of the snooze switch and displayed. The display time can be displayed in accordance with the true current time by the time set by the alarm set switch.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a digital timepiece according to the present invention, in which reference numeral 20 is a timing circuit, a reference signal generating circuit composed of an oscillator 2 and a frequency divider 4, and this reference signal. A time counter 6 for counting, an OR gate 8, a presettable counter 10, a decoder 12, and a display unit 1.
4.

An alarm circuit 50 includes a coincidence circuit 22, an alarm memory 24 for storing an alarm set time, an inverter 26, a one-shot circuit 28, two AND gates 30 and 32, and two OR gates 34. 36
And a flip-flop (hereinafter referred to as FF) 38 and a sounding circuit 40.

A snooze circuit 60 includes two AND gates 62 and 64 and two one-shot circuits 66 and 6.
8 and a counter 70. Reference numeral 80 denotes a constant pulse number output circuit, which includes two FFs 72 and 73,
AND gate 74, inverter 76, counter 78
It consists of and.

In the operation of the alarm clock with snooze having the above-mentioned structure, when the time of the clock counter 6 and the alarm memory 24 match when the alarm set switch 82 is in the ON state, the one-shot signal from the matching circuit causes the AND gate 3 to operate.
0, and is input to the C input terminal of the FF 38 via the OR gate 36. In synchronization with this rising, the Q output becomes the H level and the sounding circuit 40 issues an alarm. At this time, the clock counter 6 and the preset counter 10 indicate the same time.

When the snooze switch 84 is pushed once after an alarm is generated, the counter 70 operates via the AND gate 62 and the one-shot circuit 68, and the FF
38 is reset and sounding stops. Meanwhile counter 7
In the case of 0, the pulse is passed through the AND gate 74 until the counter 78 counts a fixed number of pulses by setting the Q output of the FF 72 to the H level and the preset counter 10 is operated after the fixed time. By being sent to, the display time is advanced by a fixed time.

After that, when the snooze switch is operated, the above-mentioned operation is repeated, and the display time is advanced by a constant time which is twice the number of times the snooze switch is operated. When the alarm sound is stopped by turning off the alarm set switch 82 while the alarm sound is being generated again, the preset counter 10 is switched to the current time display by presetting the current time of the clock counter 6. The constant pulse number output circuit may be operated by operating the snooze switch, and may be operated when the snooze switch is operated a certain number of times or more.

FIG. 2 shows a second embodiment, which is an example used for an analog timepiece. When the target is turned on while the alarm switch 82 is in the on state, the Q output of the FF 118 is set to the H level via the AND gate 108 and the OR gate 114, and the sounding circuit 120 generates an alarm sound. At this time, the counter 132 is reset and is in a state of counting the number of times the snooze switch is operated.

After that, the alarm sound is stopped by operating the snooze switch 84, and the counter 128 starts operating. Further, the counter 132 is incremented. When the snooze switch is operated a predetermined number of times, the counter 132 counts up and the AND gate 134 is opened. By the subsequent operation of the snooze switch, a fixed number of pulses are sent to the pointer counter 86 and the drive circuit 88, and the advanced time is displayed.

When the alarm set switch 82 is turned off, the inversion Q of the FF 148 for directing the direction via the AND gate 146 which is opened by the FF 144 which stores the time correction by the output from the AND gate 134 is set to L. Level, instructing reverse rotation, and resetting the FFs 170 and 172 by the H level signal of the Q output,
Further, a stepping pulse is output via the OR gate 152, the FFs 162, 164 so that the pointer counter 8 can be operated at high speed.
6. Reverse rotation correction of the train wheel 92.

When the time counter and the pointer counter 86 match, the output of the matching circuit 100 becomes H level. As a result, the Q output of the FF 170 becomes H level and the pulse output is stopped via the OR gate 150.
A second constant pulse number output circuit composed of 176, an AND gate 178, an inverter 180, and a counter 182 returns to a normal rotation by a carry signal of the counter 82 after a fixed number of steps, and a normal rotation high-speed correction signal is output from the AND gate. Is output.

After that, when the time counter and the pointer counter coincide with each other, the Q output of the FF 172 becomes H level, and the normal hand movement is resumed. The second constant pulse output circuit may be used as a delay circuit so that the high speed correction pulse is not stopped by the Q output of the FF 170. Further, to return to the current time display, a separate alarm set switch may be provided or a snooze switch operation when the alarm set switch is off may be performed.

Further, in both the first and second embodiments, the display time is advanced in proportion to the number of snooze operations, but the final alarm time is displayed by the first operation of the snooze switch and the apparatus stands by for a stop (for example, 20 minutes later). You may do it.
During this period, the snooze operation can be performed at predetermined time intervals, and the display time is set to the stopped state by displaying the last alarm time. When the current time and the display time coincide with each other by repeating the snooze operation several times, the alarm sound is made different from the normal alarm to give an alarm, and the display time starts the current time display.

The above operation is performed by AND gates 134 and 1 in FIG.
30 and the counter 132 are deleted, and instead, the output of the AND gate 124 is connected to the S input of the FF with RS and the output of the one-shot circuit 104 is connected to the R input, respectively, and the Q output of the FF 144 is set to H before the OR gate 98. In the case of, an AND gate for blocking the normal drive signal is provided, and when the alarm set switch is turned on between the matching circuit 100 and the FF170,
When a coincidence signal is generated when the Q output of F144 is H, this signal is inverted and input to the AND gate 124 to invalidate the snooze switch and input to the sounding circuit and the OR gate 114 as a signal for increasing the volume. Further, FF144 and FF148 are reset to return to the normal hand movement, and the alarm switch is turned off, so that FF144 Q
When a coincidence signal is generated when the output is H, FF17
It is possible to provide a gate circuit so as to input to the C input terminal of 0 to correct the current time display.

[0019]

As described above, according to the present invention,
Since the display time is advanced in response to the operation of the snooze switch, the wake-up alarm can be made even stronger.

[Brief description of drawings]

FIG. 1 shows an embodiment according to the present invention.

FIG. 2 shows an example of an analog timepiece according to the invention.

[Explanation of symbols]

 20 Clock circuit 50 Alarm circuit 60 Snooze circuit 80 Constant pulse number output circuit

Claims (1)

(57) [Scope of utility model registration request] 1. A snooze alarm clock which counts a reference signal to display the time, generates an alarm at a set time, and again generates an alarm after a predetermined time has elapsed after operating a snooze switch for instructing an alarm suspension. , A snooze alarm clock, which is provided with a constant pulse number output circuit that advances the display time by a predetermined time in response to the operation of the snooze switch when an alarm occurs.