JP3194857B2 - Alarm signal formation circuit for alarm clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timepiece having a timekeeping function and an alarm function, and more particularly, to an analog timepiece having an alarm function and a timepiece function. The present invention relates to a signal forming circuit.

[0002]

2. Description of the Related Art Today, an alarm-equipped timepiece is used in which an electronic sound or the like is sounded every hour to inform of the hour, and when an alarm is set, an alarm sound is emitted at an alarm set time. In the case of an analog timepiece that displays the time by hands, a minute hand or one minute in 60 minutes like a minute hand.
An hour contact is attached to the rotating gear to generate an hour signal every hour, and a time signal is generated by the hour signal. A projection is provided on the rotating reference wheel, and a reference contact provided on a contact plate that is rotatable together with the reference pointer is formed by opening and closing by the projection of the reference wheel. The alarm sounds.

Incidentally, the scale for setting the alarm time is usually set to 5 on the pointer so that one hour on the dial is divided into six equal parts.
It is provided for each degree, and a time within 12 hours is set in units of 10 minutes, and whether or not an alarm sound is sounded by a silence switch is set.

[0004]

As described above, the hour contact is mechanically turned on or off by a minute hand or a gear having a rotation speed equal to that of the minute hand. When the hour sound is generated, the alarm sound can be generated within an error range of about 10 seconds with respect to the 0 minute position of the minute hand.

On the other hand, the reference contact for forming an alarm sound is turned on or off by a reference wheel that makes one rotation in 12 hours, and the amount of rotation of the reference wheel per unit time is small, and Even if the cam position for turning on or off the contact is adjusted, the sound of the alarm sound may have an error of about several minutes from the set time. For this reason, when the alarm time is set at the correct time, the alarm sound and the alarm sound are often generated with a shift, which has a disadvantage of giving a sense of discomfort.

The present invention is intended to eliminate such a drawback and to increase the error between the sounding time of the alarm sound and the alarm set time to the sounding accuracy of the alarm sound.

[0007]

[Means for Solving the Problems]

[0008]

[0009]

[0010]

According to the present invention, an ON signal is output from a reference ON signal generation circuit that outputs an ON signal when a reference signal is input, and stops outputting an ON signal when an alarm signal is output from an alarm signal output circuit. A positive alarm pulse generation circuit that outputs a positive alarm pulse signal when a positive signal is output from a positive contact when the positive contact is output, and a switching control signal is output and switched when a positive alarm pulse signal is input A counter control circuit that outputs a storage control pulse at the start of output of the control signal and thereafter maintains the output of the switching control signal, and counts time when an ON signal is input, and the storage control pulse is input. When the switching control signal is input, when the ON signal is input, a corrected ON signal is output after a lapse of the held count value. A counter circuit, a delay circuit that outputs a second ON signal after a predetermined time has elapsed when an ON signal is input when a switching control signal is not input, and a delay circuit that outputs a modified ON signal or a second ON signal. And an alarm signal output circuit for outputting an alarm signal.

[0012] Delay The invention described in claim 1, for outputting the the indication signal is inputted indication on signal generating circuit and an ON signal and outputs an ON signal is input to the second ON signal after a predetermined time has elapsed Since the circuit includes a circuit and an alarm signal output circuit that outputs an alarm signal when the second ON signal is input, it is possible to delay the time from the output of the reference signal to the output of the alarm signal by the delay circuit. The guide pointer and the guide contact are shifted so that the guide signal is output before the hand and the hour hand match, and the guide signal can be output from the guide contact before the alarm set time.

Also, since there is an hourly alarm pulse generating circuit for outputting an hourly alarm pulse signal when an ON signal is input, an hourly alarm is output when an ON signal is output immediately before the hour. A pulse signal can be formed. Since the memory control pulse is output when the hourly alarm pulse signal is input, and the counter control circuit starts outputting the switching control signal, the memory control pulse is synchronized with the timing of the hourly signal. Can be output.

Further, since a difference counter circuit which starts counting time when the ON signal is input and holds the count value when the storage control pulse is input is provided, the output of the storage control pulse starts from the start of the output of the ON signal. The time difference up to the hour can be stored in a difference counter circuit, and the difference counter circuit outputs a corrected ON signal after a lapse of the count value when an ON signal is input when a switching control signal is input. Therefore, a corrected ON signal delayed from the ON signal by a time equal to the time difference between the ON signal and the positive pulse signal can be formed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A reference circuit having the same effects as the alarm signal forming circuit according to the present invention has a form as shown in FIG.
1, reference ON signal generation circuit 25, alarm signal output circuit 4
1 and a time signal output circuit 35.
The pulse generator 23 serving as the positive pulse generating circuit 21 includes a reset input terminal of a timer 33 having an input terminal connected to the positive contact 11 and an output terminal serving as a timing control circuit 31, and a time signal output circuit. 35 and an input terminal of an AND circuit 37.

Therefore, the pulse generating circuit 21
Is turned on, an H-pulse is output to output an hour pulse signal in synchronization with the timing of the generation of the hour signal. A timer for the timing control circuit 31
33 uses a 10-minute counter, outputs an H level carry signal from the first output terminal to the C signal when the count value is 0, and outputs an H level sub carry signal from the second output terminal when the count value is 5; It outputs to the D signal.

Accordingly, as shown in FIG. 2, the timing control circuit 31 is reset every 60 minutes in response to the generation of the hour signal by the input of the hour pulse signal, and the C signal at the first output terminal is: A pulse is output at a predetermined interval of 10 minutes from the generation of the hour signal, and the first pulse is output to the D signal of the second output terminal 5 minutes after the generation of the hour signal, which is 1/2 of the predetermined interval. After that, a pulse is output at an interval of 10 minutes, and the reference of the pulse output of the first timing signal, which is the C signal, and the second timing signal, which is the D signal, is positive every hour. This is when the time pulse signal is input.

The first output terminal of the timer 33 is connected to the alarm signal output circuit 41, and the second output terminal is connected to the reference ON signal generation circuit 25. This reference ON signal generation circuit 25 is composed of a D-flip-flop 26 and an OR circuit.
27, the D input terminal of the first D-flip-flop 26 is used as a reference contact 13, the C input terminal is used as the timing control circuit 31, the second output terminal of the timer 33 is used, and the Q output terminal is used as an alarm signal output. The input terminal of the AND circuit 43 in the circuit 41 is connected to the negative input terminal of the AND circuit 37 serving as the time signal output circuit 35, and the reset input terminal is connected to the output terminal of the OR circuit 27 of the reference ON signal generation circuit 25, The input terminal of the OR circuit 27 is connected to the output terminal of the AND circuit 43 in the alarm signal output circuit 41 and the silence switch 15.

Therefore, the reference ON signal generation circuit 25
When the reference contact 13 is in the off state, the F signal which is the Q output is always at the L level. When the reference contact 13 is turned on and the pulse is output from the timer 33 to the second timing signal, the F signal is at the H level. Is output.
The alarm signal output circuit 41 is composed of an AND circuit 43 and a D-flip-flop 45, and a first output terminal of the timer 33 having the input terminal of the AND circuit 43 as the timing control circuit 31 and a reference ON signal generation circuit. 25 and the Q output terminal of the first D-flip-flop 26 in the
Output terminal of the alarm signal output circuit 41
It is connected to the C input terminal of the D flip-flop 45 and the OR circuit 27 in the reference ON signal generation circuit 25.

The second D-flip-flop 45
The D input terminal is connected to an H level power supply, the Q output terminal is connected to an alarm signal output terminal 17, and the reset input terminal is connected to a silence switch 15. Therefore, when the ON signal from the reference ON signal generation circuit 25 is input to the AND circuit 43, the alarm signal output circuit 41
When a pulse is output to the first timing signal, which is a signal, the AND circuit 43 passes the pulse of the first timing signal, outputs an H pulse to the G signal, and outputs the Q output of the second D-flip-flop 45 to the H level. An alarm signal is output to the J signal as a level, and the first D-flip-flop in the reference ON signal generation circuit 25 is output by an H pulse of the G signal.
This resets 26 to stop the output of the ON signal.

When the ON signal is output from the reference ON signal generation circuit 25, the notification signal output circuit 35 cuts off the positive pulse signal from the positive pulse generation circuit 21 and outputs the ON signal. Only when this is not the case, an hour pulse signal indicating the generation timing of the hour signal is output to the time signal output terminal 19 as a time signal. Thus, the reference circuit
So hour pulse in accordance with the occurrence of the hour signal generating circuit 21
The timing control circuit 31
Set the timer 33 to 6 according to the timing of the hour signal.
The timer 33 resets the timer every 0 minutes.
A first timing signal for outputting a pulse at an interval of 10 to 10 minutes is formed, and a second timing signal for outputting a pulse at an interval of 5 minutes and 5 to 10 minutes is formed. Since the reference signal is latched by the first D-flip-flop 26 of the circuit 25, the reference contact 13 is switched between 5 and 15 minutes, between 15 and 25 minutes, between 25 and 35 minutes, between 35 and 45 minutes, and between 45 and 45 minutes. When the ON state is set between the minutes and 55 minutes, or between 55 minutes and 5 minutes, the output of the ON signal is started at the break time of each time. For example, as shown in FIG. About 20 minutes after the time, when the reference contact 13 is turned on and the reference signal is output to the E signal, the ON signal is turned on by the H pulse of the second timing signal output at 25 minutes. When the H signal is output as the first timing signal after the F signal which is the output of the signal generation circuit 25 and the ON signal is output, that is, when 30 minutes have elapsed from the output of the positive pulse signal The alarm signal output circuit 41 outputs an alarm signal.

In this reference circuit , the silence switch 15
Resets the second D-flip-flop 45 in the alarm signal output circuit 41 to stop the output of the alarm signal. In this way, the start of the output of the alarm signal can be synchronized with the pulse output of the pulse set at the predetermined interval output as the first timing signal,
Since the first timing signal is formed as a predetermined time interval by the timer 33 which is reset every 60 minutes in accordance with the generation of the hour signal by the hour pulse signal, the standard contact 13 is turned on and the standard signal becomes Even if the output timing varies, the start of sounding of the alarm by the alarm signal can be accurately adjusted to 0 minute, which is the generation timing of the hour signal, and the alarm sound is generated at a relatively accurate time in units of 10 minutes. Can be started, and the reference contact 13 is set to 10 at a position where the reference hand and the hour hand match.
If the mounting angle of the guide pointer and the position of the guide contact 13 are adjusted so that the switch is turned on about a minute earlier,
Is turned on and the reference signal is output, then the pulse of the second timing signal is output, and when the pulse of the first timing signal is output, the output of the alarm signal is started. The alarm time can be set.

The timer used as the timing control circuit 31
33 is not limited to a 10-minute counter, and a time error when the reference contact 13 is turned on due to a mechanical error when the reference contact 13 is attached is within 2 minutes 30 seconds from a set time. In the case of accuracy, a 5-minute counter is used as the timer 33, and the pulse interval of the first timing signal and the pulse interval of the second timing signal are set to 5 minutes, which is half of the predetermined time, 2 minutes 30 seconds. Is set as the time difference between the pulse of the first timing signal and the pulse of the second timing signal, thereby setting the alarm time to 5 times.
The interval can be set in minutes, and the interval between the pulses of the first timing signal and the pulses of the second timing signal is changed and set so as to be wider or narrower in accordance with the accuracy of the reference contact 13.

If the timing control circuit 31 uses a 10-minute counter to set the start of alarm sounding in units of 10 minutes, the rotation of the reference setting knob is provided with irregularities that give a click feeling at intervals of 5 degrees. The setting of the alarm time can be made easier and more accurate. In addition, as shown in FIG.
In the reference circuit, a time signal output circuit 35 is provided, but in the alarm signal forming circuit having the timer 33 as the timing control circuit 31, the reference ON signal generation circuit 25, and the alarm signal output circuit 41, an alarm is generated at the correct time. If set,
The timer 33 is reset by the positive pulse signal and the first
Since the output of the alarm signal is started by the pulse of the timing signal, the time signal output circuit 35 is omitted, and the positive pulse signal output from the positive pulse generation circuit 21 or the positive signal output from the positive contact 11 is output. , The time signal and the alarm start sounding at the same time even when the time signal is sounded as the time signal as it is.

In the embodiment of the present invention , as shown in FIGS. 3 and 4, the positive pulse generator 21, the reference ON signal generator 25, the time signal output circuit 35, and the alarm signal output circuit 41 are used. In addition, the positive alarm pulse generator 61 and delay circuit
51, a counter control circuit 65, a difference counter circuit 71, and a reset control circuit 81. As shown in FIG. 3, the hour pulse generating circuit 21 uses a D-flip-flop or forms an hour pulse when an hour signal is generated using an appropriate pulse generator. The output terminal of the positive pulse generating circuit 21 is connected to the input terminal of an AND circuit 37 serving as a time signal output circuit 35 and the input terminal of the AND circuit 62 of the positive alarm pulse generating circuit 61. .

The reference ON signal generation circuit 25 includes a D
-Using a flip-flop and an OR circuit, this 3D-
The D input terminal of the flip-flop 28 is connected to an H level power supply,
Connect the input terminal to the reference contact 13, connect the Q output terminal and
The output terminal is connected to the delay circuit 51, and the Q output terminal is connected to the input terminal of the AND circuit 62 in the hourly alarm pulse generating circuit 61 and to the negation of the AND circuit 37 which is a difference counter circuit 71 and a time signal output circuit 35 described later. The reset input terminal of the third D-flip-flop 28 is connected to the output terminal of the first OR circuit 29, and the input terminal of the first OR circuit 29 is connected to the reset control circuit 81, the silence switch 15, Is to be connected to.

Accordingly, when the reference contact 13 is turned on and a reference signal is input, the reference ON signal generating circuit 25 in this embodiment, as shown in FIG. A low-level ON signal is output, and an L-level ON signal is output to the F ′ signal which is an inverted Q output. The delay circuit 51 is composed of two AND circuits and one timer. One input terminal of the third AND circuit 53 is connected to the third D signal in the reference ON signal generation circuit 25.
The clock signal is input to the Q output terminal of the flip-flop 28, the other input terminal of the third AND circuit 53 is connected to the appropriate reference frequency signal output terminal, and the output terminal of the third AND circuit 53 is To the clock input terminal of the delay timer 55, the carry output terminal of the delay timer 55 to the input terminal of the fourth AND circuit 57, the negative input terminal of the fourth AND circuit 57 to the counter control circuit 65 described later, and the fourth AND circuit. 57
Are connected to an alarm signal output circuit 41 to be described later, and a reset input terminal of the delay timer 55 is connected to the inverted Q output terminal of the third D-flip-flop 28 in the reference ON signal generation circuit 25.

Accordingly, when the H-level ON signal output from the reference ON signal generation circuit 25 is input, the delay circuit 51 opens the third AND circuit 53 and inputs a clock signal to the delay timer 55, At this time, the delay timer 55 has L
When the level ON signal is input and the count is possible, the delay timer 55 outputs a carry signal after a predetermined time, and when the H level switching control signal is not input from the counter control circuit 65, it passes through the fourth AND circuit 57. This carry signal is output, and a second ON signal at a timing delayed from the rise of the ON signal by the set time of the delay timer 55 is output to the M signal output from the delay circuit 51.

The hourly alarm pulse generating circuit 61 comprises an AND circuit and a D-flip-flop. The input terminal of the fifth AND circuit 62 has an output terminal of the hourly pulse generating circuit 21 and a reference ON signal generating circuit. 25, is connected to the Q output terminal of the third D-flip-flop 28, the output terminal of the fifth AND circuit 62 is connected to the C input terminal of the fourth D-flip-flop 63, and the D input terminal of the fourth D-flip-flop 63 To H
The Q power terminal of the fourth D-flip-flop 63 is connected to the counter control circuit 65 to be described later, and the level power supply is also connected to the reset input terminal of the fourth D-flip-flop 63.

Therefore, the hourly alarm pulse generating circuit
Numeral 61 indicates that when the positive pulse generating circuit 21 outputs a positive pulse signal while the reference ON signal generating circuit 25 is outputting an ON signal, an H pulse positive alarm pulse signal is output from the Q output terminal. It is. Further, the counter control circuit 65
Is composed of an AND circuit and a D-flip-flop. The input terminal of the ninth AND circuit 66 is connected to the Q output terminal of the fourth D-flip-flop 63 in the positive alarm pulse generating circuit 61. Is connected to the Q output terminal of the fifth D-flip-flop 67 of the counter control circuit 65, and the output terminal of the ninth AND circuit 66 is connected to the fifth D-flip-flop 67.
It is connected to the C input terminal of the flip-flop 67 and to a difference counter circuit 71 and an alarm signal output circuit 41, which will be described later. The D input terminal of the fifth D-flip-flop 67 is an H level power supply, and the Q output terminal is a ninth AND terminal. In addition to the circuit 66, it is connected to the delay circuit 51 and a difference counter circuit 71 described later.

Although not shown, the reset input terminal of the fifth D-flip-flop 67 is appropriately connected to a reset switch. Therefore, when the positive alarm pulse signal from the positive alarm pulse generating circuit 61 is input when the fifth D-flip-flop 67 is in the reset state, the counter control circuit 65 changes the positive alarm pulse signal to the fifth D-flip-flop 67. The signal is input to the C input terminal of the flip-flop 67, the Q output is switched to the H level, and the control signal is switched to the P signal. Thereafter, the ninth AND circuit 66 is closed to interrupt the input of the normal alarm pulse signal. Only the positive alarm pulse signal is input to the fifth D-flip-flop 67, and this pulse is also output to the difference counter circuit 71 as a storage control pulse, and this storage control pulse is also output to the alarm signal output circuit 41. .

As shown in FIG. 4, the difference counter circuit 71 includes three AND circuits, one latch circuit 74 and a pulse generator, and an up counter 73 and a down counter.
78. This difference counter circuit 71
The input terminals of the sixth AND circuit 72 and the seventh AND circuit 75 and the reset input terminal of the up counter 73 are connected to the Q output terminal of the third D-flip-flop 28 in the reference ON signal generation circuit 25, and the sixth AND circuit 72 and 8th AND circuit 77
The other input terminal is connected to an appropriate reference frequency signal output terminal, and the input terminal of the seventh AND circuit 75 and the reset input terminal of the down counter 78 are connected to the fifth input terminal of the counter control circuit 65.
Connected to the Q output terminal of D-flip-flop 67,
The output terminal of the sixth AND circuit 72 is connected to the clock input terminal of the up counter 73, and the count data output terminal of the up counter 73 is connected to the preset data input terminal of the down counter 78 via the latch circuit 74. Is connected to the input terminal of the eighth AND circuit 77 and the pulse generator 76.
The output terminal of the eighth AND circuit 77 is the clock input terminal of the down counter 78, the output terminal of the pulse generator 76 is the preset control terminal of the down counter 78, and the borrow signal output terminal of the down counter 78 is the alarm. The signal output circuit 41 and the latch control signal terminal of the latch circuit 74 are connected to the output terminal of the ninth AND circuit 66 in the counter control circuit 65.

Therefore, in the difference counter circuit 71, when the ON signal is input, the sixth AND circuit 72 is opened, the up counter 73 counts the duration of the ON signal, and when the input of the ON signal is stopped. Closing the sixth AND circuit 72 and resetting the up counter 73 are repeated. Then, when a storage control pulse or a switching control signal is input from the counter control circuit 65, the count value of the up counter 73 is latched in the latch circuit 74 by the storage control pulse,
The switching control signal allows the down counter 78 to count and opens the seventh AND circuit 75.

Accordingly, the count value latched by the latch circuit 74 in the difference counter circuit 71 is determined from when the reference ON signal generation circuit 25 starts outputting the ON signal to when the counter control circuit 65 outputs the storage control pulse. The time is a value corresponding to the time difference from the start of the output of the ON signal to the output of the positive alarm pulse signal. Further, when the ON signal is input while the input of the switching control signal is continued after the input of the switching control signal is started, the ON signal passes through the opened seventh AND circuit 75, Pulse generator 76 outputs pulses and counts down
The count value of the latch circuit 74 is preset to 78, and the eighth AND circuit 77 is opened to input a clock signal from the reference frequency output terminal to the down counter 78 to start down counting.

Then, after the count value of the down counter 78 becomes 0, the down counter 78 outputs an H pulse borrow signal as a modified ON signal as the S signal. The corrected ON signal is output after the down counter 78 subtracts the value of the latch circuit 74 and becomes 0. The preset value of the down counter 78 is obtained by the up counter 73 when the output of the ON signal is started. The difference from the time when the positive alarm pulse signal is output, that is, a value corresponding to the time difference between the start of the output of the ON signal and the start of the output of the positive pulse signal, and the count value is subtracted by the same clock. Counter circuit 71
Can output a modified ON signal delayed from the start of the output of the ON signal by a time difference equal to the time difference between the start of the output of the ON signal and the start of the output of the positive pulse signal.

The alarm signal output circuit 41 comprises an OR circuit and a D-flip-flop, as shown in FIG. 3, and each input terminal of a three-input second OR circuit 44 is a difference counter. The borrow signal output terminal of the down counter 78 in the circuit 71, the output terminal of the fourth AND circuit 57 in the delay circuit 51, and the ninth AND circuit in the counter control circuit 65
66, the output terminal of the second OR circuit 44 is connected to the reset control circuit 81 and the C input terminal of the sixth D-flip-flop 46 in the alarm signal output circuit 41, and the sixth D-flip-flop 46 is connected. The D input terminal is connected to an H level power supply, the reset input terminal is connected to a silence switch 15, etc., and the Q output terminal is connected to an alarm signal output terminal 17.

Therefore, this alarm signal output circuit 41
A corrected ON signal which is a pulse signal from the difference counter circuit 71, a second ON signal which is a pulse signal from the delay circuit 51, or a storage control pulse which is a pulse signal from the counter control circuit 65 is input. The second OR circuit 44
A modified ON signal, a second ON signal, or a memory control pulse is output as an alarm start pulse to the 6D-flip-flop 46 via the 6D-flip-flop 46.
The Q output of the flip-flop 46 is set to the H level to output an alarm signal as a J signal, and also outputs an alarm start pulse to the reset control circuit 81.

The reset control circuit 81 comprises a D-flip-flop, an AND circuit, and a timer, as shown in FIG. 4, and connects the C input terminal of the seventh D-flip-flop 83 to the alarm signal output circuit 41. The second OR circuit 44 in
, The D input terminal of the seventh D-flip-flop 83 to the H level power supply, and the Q output terminal to the tenth AND circuit 85.
Connected to the reset input terminal of the second delay timer 87, the other input terminal of the tenth AND circuit 85 is connected to the appropriate reference frequency signal output terminal, and the output of the tenth AND circuit 85 The terminal is connected to the clock input terminal of the second delay timer 87, the carry signal output terminal of the second delay timer 87 is connected to the reset input terminal of the seventh D-flip-flop 83 in the reset control circuit 81 and the reference ON signal generation circuit.
25 is connected to the reset input terminal of the third D-flip-flop 28.

Therefore, when the alarm start pulse is output from the alarm signal output circuit 41, the reset control circuit 81 sets the Q output of the seventh D-flip-flop 83 to the H level to open the tenth AND circuit 85, The output is set to L level, and the second delay timer 87 can be counted.
The delay timer 87 counts the clock signal from the reference frequency signal output terminal, and outputs a carry signal as a U signal to reset the third D-flip-flop 28 and the seventh D-flip-flop 83 when a predetermined time has elapsed. .

The set time of the second delay timer 87 is shorter than the set time of the delay timer 55 in the delay circuit 51. Thus, in this alarm signal forming circuit, when the fifth D-flip-flop 67 in the counter control circuit 65 is in the reset state and the switching control signal is not output from the counter control circuit 65, the reference contact 13 is turned on. When the reference signal is input to the reference ON signal generation circuit 25, an ON signal is output from the reference ON signal generation circuit 25, and the second ON signal is output from the delay circuit 51 with a delay time set by the delay circuit 51. Is output, an alarm signal is output from the alarm signal output circuit 41, and the third D-flip-flop 28 in the reference ON signal generation circuit 25 is reset with a delay of a time set in the reset control circuit 81, and the reference ON signal is output. The output of the ON signal from the generation circuit 25 is stopped.

Accordingly, the reference pointer and the reference contact are set so that the time at which the reference contact 13 is turned on is earlier than the coincidence time between the reference pointer and the hour hand by the delay time set by the delay circuit 51.
If it is shifted from 13, the alarm can be sounded when the reference hand and the hour hand coincide with each other as in the conventional case. Then, when the alarm time is set to the hour at the hour according to the guideline, the indicator contact 13 is turned on before the hour and an ON signal is output from the indicator ON signal generation circuit 25, and the ON signal is output. When the hour contact 11 is turned on during the output, the hour pulse signal is output from the hour pulse generating circuit 21, and the hour alarm pulse generating circuit 61 outputs the hour alarm pulse signal.

As described above, the hourly alarm pulse generating circuit
When the positive alarm pulse signal is output from the counter 61, the counter control circuit 65 outputs a storage control pulse to cause the latch circuit 74 to latch the count value of the up counter 73, and the count value of the down counter 78 is changed by the switching control signal. In this case, the count value is preset and the countdown is performed. Further, the fourth AND circuit 57 of the delay circuit 51 is closed by the switching control signal, and the storage control pulse is also output to the alarm signal output circuit 41.

When the second ON signal from the delay circuit 51 is output from the delay circuit 51 before the positive pulse signal, the alarm signal output circuit 41 is output by the second ON signal.
An alarm signal is output from the reset control circuit 81, and when the time set in the reset control circuit 81 has elapsed, the output of the ON signal output from the reference ON signal generation circuit 25 is stopped, and the count of the down counter 78 is stopped. is there.

Since the counter control circuit 65 maintains the output of the switching control signal thereafter, the fourth AND circuit 57 of the delay circuit 51 to which the switching control signal is input is closed.
The delay circuit 51 does not output the second ON signal. When the second ON signal from the delay circuit 51 is output from the delay circuit 51 after the output of the positive pulse signal, the fourth AND circuit 57 is closed and the second ON signal from the delay circuit 51 is output. Is output, the stored control pulse output from the counter control circuit 65 is input to the alarm signal output circuit 41 in synchronization with the output timing of the hour pulse signal, and the alarm signal output circuit 41 generates the hour signal. An alarm signal is output according to the timing.

Next, when an alarm is set and the reference ON signal generating circuit 25 outputs an ON signal, the seventh AND circuit 75 in the difference counter circuit 71 is opened by the switching control signal. When an ON signal is input to the circuit 75, the pulse generator 76 outputs a pulse signal to cause the down counter 78 to read the count value of the latch circuit 74, and the eighth AND circuit 77 is opened to perform down counting. After a predetermined time, the correction ON signal is output.

The time difference between the input of the ON signal and the output of the corrected ON signal in the difference counter circuit 71 is determined by the time when the standard signal is set to 0 minute and the normal signal is turned on after the standard contact 13 is turned on. Since it is equal to the time difference until output, once the time of the hour is set as the alarm time, the time difference between the time when the reference contact 13 is turned on and the time indicated by the minute hand is calculated by the difference counter circuit 71. The corrected ON signal is output after the correction, the alarm sounding start time can be adjusted to the correct coincidence time between the reference hand and the hour hand, and the guide pointer is set to the alarm time in units of 5 minutes or 10 minutes by the click mechanism. By incorporating this alarm signal forming circuit into the obtained clock body, an alarm sound can be generated at a relatively accurate alarm time.

[0047] Then, in this embodiment, the provided time signal output circuit 35, the time distribution to close the AND circuit 37 which is a time signal output circuit 35 by the ON signal outputted from the guideline on signal generation circuit 25 Although the signal is not output, the time signal output circuit 35 can be omitted as in the reference circuit shown in FIG. Further, in the above-described embodiment, the time difference between the output start time of the reference signal and the time when the hour hand matches the reference pointer due to the difference between the reference pointer and the reference contact 13 is substantially the same as the delay time by the delay circuit 51 or the delay time. Although the time is set to be longer than the time, the delay time set in the delay circuit 51 is set to be smaller than the time when the hour hand matches the reference pointer 13.
If the time difference is set to be larger than the time at which the switch is turned on earlier, the fourth AND circuit 57 and the reset control circuit 81 in the delay circuit 51 can be omitted as shown in FIG. Control pulse to alarm signal output circuit 41
Can also be omitted.

However, the alarm signal forming circuit provided with the reset control circuit 81 shown in FIGS. 4 and 5 makes the delay time of the delay circuit 51 substantially equal to the difference between the output time of the reference signal and the alarm setting time according to the reference guideline. Even when the second ON signal is output slightly earlier than the output of the hour signal, the hour alarm pulse signal can be reliably formed and the difference counter circuit 71 can be set. .

[0049]

According to the first aspect of the present invention, at the time of the hour,
If you set an alarm and use the alarm once,
Enables accurate sounding of alarm sounds at alarm set times
This makes it possible to eliminate a time lag between the sound of the alarm sound and the sound of the alarm sound .

[0050]

[0051]

[Brief description of the drawings]

FIG. 1 shows the same reference as the alarm signal forming circuit according to the present invention.
FIG. 2 is a block diagram showing an example of a circuit .

FIG. 2 is a circuit diagram similar to the alarm signal forming circuit according to the present invention;
FIG. 4 is a time chart showing each signal in a circuit example .

The in alarm signal forming circuit according to the present invention; FIG
FIG. 1 is a block diagram showing an embodiment.

The in alarm signal forming circuit according to the present invention; FIG
FIG. 1 is a block diagram showing an embodiment.

FIG. 5 is a time chart showing signals in the alarm signal forming circuit according to the first embodiment of the present invention;

The in alarm signal forming circuit according to the present invention; FIG
FIG. 9 is a block diagram showing a second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Hour contact 13 Estimated contact 15 Sound stop switch 21 Hour pulse generation circuit 25 Estimation ON signal generation circuit 31 Timing control circuit 35 Alarm signal output circuit 41 Alarm signal output circuit 51 Delay circuit 61 Hour alarm pulse generation circuit 65 Counter Control circuit 71 Difference counter circuit 81 Reset control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G04G 13/00-13/02 G04C 21/02-21/28

Claims (1)

(57) [Claims] An on signal is output from a reference on signal generating circuit.
Hour signal is output from the hour contact when power is applied
And an hourly alarm pulse that outputs an hourly alarm pulse signal
Signal and a switching control signal when a positive alarm pulse signal is input.
Is output and storage control is performed when the switching control signal is output.
Output a pulse and then maintain the output of the switching control signal
A counter control circuit that counts time when an ON signal is input, and
Holds the count value when the control pulse is input and switches
When the control signal is input, the ON signal is input.
The corrected ON signal after the time of the held count value elapses.
An output difference counter circuit and an ON signal when a switching control signal is not input
Output, the second ON signal is output after a predetermined time has elapsed.
An alarm signal forming circuit for an alarm-attached timepiece, comprising: an extension circuit; and an alarm signal output circuit that outputs an alarm signal when a modified ON signal or a second ON signal is input .