JPH04135275A - Pipeline control system - Google Patents

Abstract

PURPOSE:To detect trouble of a control circuit at the time of a clock stop in its early stage by providing a clock stop means which stops a clock forcibly from outside by an integral multiple of the number of interleaved pulses. CONSTITUTION:A clock stop circuit 12 outputs one pulse after stopping the clock by an integral multiple of the number of interleaved pulses, and the integer can be set from outside. Therefore, the clock period is delayed by the integral multiple of the number of interleaved pulses. A selecting circuit 13 performs stop control over arithmetic pipelines 3-1 - 3-m, a vector register 2, an instruction control part 6, etc., normally according to a signal sent from a stop signal generation part 5, but performs the stop control over them according to a signal sent from the clock stop circuit 12 once an external setting signal is sent. Consequently, the trouble can be detected in its early stage.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 3 to 6) Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Working Examples (Figure 2) Effects of the invention [Summary] Regarding the pipeline control method, the present invention makes it possible to detect logical contradictions or failures in the control circuit that controls the stopping of the calculation pipeline and the logic circuit that stops the processing pipeline at an early stage, for example, at the test stage. at least one or more access pipelines;
a vector processing device having one or more arithmetic pipelines and interleaved vector registers;
one or more main storage devices and a memory access control device for controlling memory access from an access pipeline, and register chaining of data loaded from the main storage device to a vector register by the access pipeline. control so as to sequentially supply data to the arithmetic pipeline, and to stop the clock of the arithmetic pipeline by the number of vector registers to be interleaved when the data to be loaded from the main memory to the vector register is exhausted. In this vector processing device, a clock stop means for forcibly stopping the clock by an integer multiple of the number of interleaves is provided from the outside, so that a failure in the control circuit at the time of clock stop can be detected at an early stage.

[Industrial application field]

The present invention relates to a load access pipeline and a stop control method for an arithmetic pipeline when the arithmetic pipeline performs a link operation in a vector processing device equipped with a vector register.

[Conventional technology]

The vector calculation device is CPLJ20 as shown in Figure 3.
, a vector unit 21, one or more main storage devices 22-0.22-1-, and a memory control device 23. Then, the vector unit 21 includes a plurality of vector registers VRo, VR5 ---, and an arithmetic unit LU.
Equipped with O, LUI.

The vector registers are interleaved into eight banks, bank 0, bank 1-bank 7, as shown in FIG. Note that FIG. 4 is an explanatory diagram of the connection state of the vector register VRo shown in FIG. 3 and its peripheral circuits. It has a vector load section 30-0.30-1 for writing, and a selection section 31-0.31-1 for selectively reading out elements to be computed by the arithmetic unit LUO from banks 0 to 7.

Now, a case will be described in which a command as shown in the upper right corner of FIG. 5 is executed. Here, VL indicates vector load, VAD indicates addition, and VRa is loaded as vector A and VRb is loaded as vector B into the vector register, respectively.
It shows that these are added.

Therefore, as shown in FIG. 5, in the 10th pipeline, in order to load vector A,
Address conversion (logical address - real address), ■Memory access, ■Memory activation, ■Data fetch, and ■Vector register bank write are performed. This is the first
Vector load section 3 whose 0-do pipeline is shown in FIG.
If it is set to 0-0, the above processing is performed by this vector load section 3o-0 and the memory control device.

Also, the 20th pipeline is connected to the vector load unit 30.
If it is set to -1, the vector B is loaded in parallel with the loading of the vector A by the vector loading unit 30-1 or the like.

VRa and VRb loaded into the vector register are read out by the selection unit 31-0.31-1, and the addition stage shown in FIG. 5 is executed by the arithmetic unit LLIO.

By the way, the arithmetic pipeline is configured to continuously process the data on the vector register, but the access pipeline cannot necessarily continuously supply the desired data to the vector register because memory access contention occurs in the memory control unit. Not necessarily.

Therefore, when both pipelines are linked, in which the load pipeline loads data into a hector register, and the arithmetic pipeline reads it and processes it, the discontinuity in the data supply of the load pipeline causes , there is a risk of overtaking the data writing of the calculation pipeline.

In order to avoid this, it is sometimes necessary to stop the arithmetic pipeline by the amount of vector register interleaving (eight cycles in the example of FIG. 4) to synchronize the pace of both vibe lines.

FIG. 6 is a block diagram showing pipeline control in a conventional vector processing device.

In FIG. 6, reference numerals 1-1 to 1-n are load access pipelines, which transfer data between a storage device (not shown) and the vector register 2. In FIG.

Reference numeral 2 denotes a vector register, which is a group of registers that hold data before, during and after an operation, and can be accessed at high speed.

3-1 to 3-m are calculation pipelines that perform calculations while reading data from the vector register 2, and write iX results to the vector register 2.

4-1 to 4-n are calculation pipeline stop request generation units; 5
Reference numeral 6 indicates an arithmetic vibration line stop signal generating section, and 6 indicates an instruction control section.

In the load access pipelines 1-1 to 1-n,
When a load instruction is being executed and load data can be written into the vector register 2, the load data write notice signals 7-1 to 7-n are turned on and valid, for example.

That is, the memory control device notifies the load access pipeline that made the access request of a signal that memory access has been performed, so that the load vibe line is activated by the load data write notice signals 7-1 to 7-.
It becomes possible to turn on (enable) n.

The load access pipelines 1-1 to 1-n do not wait for the execution of the load instruction being executed to complete, and the load access pipelines 1-1 to 1-n transfer the data being written to the calculation pipelines 3-1 to 3-3. When in the link operation mode used by m, the link signals 8-1 to 8-n are on.

The calculation pipeline stop request generating units 4-1 to 4n monitor the load data write notice signals 7-1 to 7n and the link signals 8-1 to 8-n, and the link signals 8-1 to 8
When -n is valid, load data write notice signal 7-
1 to 7-n become invalid, the arithmetic pipeline stop request generators 4-1 to 4-n generate an arithmetic pipeline stop request signal to the arithmetic pipeline stop signal generator 5.

The arithmetic pipeline stop signal generator 5 monitors each stop request from the arithmetic pipeline stop request generators 4-1 to 4-n, and if even one request is generated, the arithmetic pipeline stop signal 9 is generated. is turned on and enabled, and the calculation pipelines 3-1 to 3-m are stopped.

In addition, in the arithmetic pipeline stop signal generation unit 5, even if the stop request disappears, the arithmetic pipeline stop signal is generated until the timing when the arithmetic pipelines 31 to 3-m access the interleaved vector register 2. 9 is turned off and controlled so that it does not become invalid.

Further, this arithmetic pipeline stop signal 9 is transmitted to the vector register 2, so that when the arithmetic pipelines 3-1 to 3-m are stopped, the register addresses of the vector register 2 are not updated.

The command control unit 6 performs command transmission control, and receives the signal 1
Load access pipeline 1-1 to 1 by 0.11
-n, which controls the arithmetic pipelines 3-1 to 3-m, but when the arithmetic pipelines 3-1 to 3-m are stopped, commands are issued by the arithmetic pipeline stop signal 9. Controlled not to make outgoing calls.

[Problem to be solved by the invention]

In the conventional system shown in FIG. 6, the arithmetic pipeline stop signal 9 output from the arithmetic pipeline stop signal generator 5 causes the arithmetic pipelines 3-1 to 3-m to stop.
It is necessary to perform complex controls such as controlling the address update of the vector register 2 and controlling the command transmission of the command control unit 6.
Therefore, the instruction control unit 6 at the time of cross-extension of the calculation pipelines 3-1 to 3-m, the calculation pipelines 3-1 to 3-m
-m has a problem in that it is difficult to detect failures in control circuits such as the stop control circuit at an early stage.

[Means to solve the problem]

Therefore, in the present invention, as shown in FIG. 1, a clock stop circuit 12 and a selection circuit 13 are provided.

The clock stop circuit 12 outputs one pulse after stopping the clock by an integer multiple of the number of interleaves, and is configured so that the value of the integer can be set externally. Therefore, the clock period is delayed by an integral multiple of the interleaving number.

In normal cases, the selection circuit 13 selects the calculation pipelines 3-1 to 3- based on the signal transmitted from the stop signal generator 5.
Stop control of the m1 vector register 2, instruction control unit 6, etc. is performed based on a signal transmitted from the clock stop circuit 12 when an external setting signal is transmitted.

[Effect]

Therefore, normally the clock stop circuit can be operated in the same manner as the conventional one shown in FIG.
2 and selection circuit 13 to increase the period of the clock by an integral multiple of the number of interleaves and control it to a slow operating state. Based on this, for example, each part can be checked accurately at the test stage. is possible,
Deficiencies can be detected early.

〔Example〕

An embodiment of the present invention will be described based on FIG.

In FIG. 2, the same symbols as in FIGS. 1 and 6 indicate the same parts.

In FIG. 2, 1-1 to 1-n are load access pipelines. 2 is a vector register, 3-1
~3-m is an arithmetic pipeline.

4-1 to 4-n are arithmetic pipeline stop request generation units, 5 is an arithmetic pipeline stop signal generation unit, and a stop request is received from any of the arithmetic pipeline stop request generation units 4-1 to 4-n. When the signal is output, an arithmetic pipeline stop signal is output, and the operation of the arithmetic pipelines 3-1 to 3-m is controlled to be stopped. Of course, at this time, the operations of the vector register 2 and the instruction control section 6 are also stopped.

Reference numeral 6 denotes an instruction control unit which performs instruction transmission control, and for example, uses a signal 10.11 to control the load access pipeline 1-1.
.about.l-n, to control the transmission of instructions to the calculation pipelines 3-1 to 3-m.

Reference numeral 12 denotes a clock stop circuit, which stops the clock by an integer multiple of the number of interleaves specified from the outside. Therefore, the counter 12-L subtraction unit 12
-2, a multiplication section 12-3, a register 12-4, and the like. The multiplier 123 receives the interleaving number "8" and multiplies it by the externally set value in the register 12-4.
Counter 12-1 is initialized to this multiplied value.

Then, this initial setting value is converted to r-IJ by the subtraction unit 12-2.
When m is calculated and becomes zero, clock stop circuit 1
2 outputs one pulse.

Reference numeral 13 denotes a selection circuit, which normally outputs the signal transmitted from the stop signal generator 5, but outputs the signal transmitted from the clock stop circuit 12 when an external setting signal is input.

As mentioned above, since the selection circuit 13 normally outputs the signal from the stop signal generating section 5, it operates in the same manner as the conventional circuit shown in FIG.

By the way, if the existence of a defect is expected for some reason, such as during the design stage or test stage, a numerical value "2", for example, is set in the register 12-4 using an external setting signal. As a result, the multiplier 123 calculates 2X8=16, the counter 121 is initialized to 16, and the clock stop circuit 12 outputs a clock stop signal. This clock stop signal is transmitted to the arithmetic pipelines 3-1 to 3-m, the vector register 2, and the instruction control unit 6 via the selection circuit 13, and the operation is stopped. And Kanuta 12-1 is “-1” by the clock.
” is subtracted and when it becomes zero, clock stop circuit 1
One clock is output from 2. As a result, the operation stop state is released by one clock, and the operation becomes the stop state again. That is, as a result, each section is controlled by a clock whose cycle is slowed down by the value calculated by the multiplier 12-3. Therefore, each part can be accurately diagnosed during this time. For example, if a part that is not supposed to work is working during the clock stop period,
Can be checked correctly.

Of course, the integer set in the register 12-4 is not limited to a specific value, and can be selected as appropriate.

〔Effect of the invention〕

According to the present invention, the clock stop period can be freely given by an external setting signal, so by selecting it according to the object to be checked, it is possible to accurately check for failures in various parts when the clock is stopped. . Therefore, it becomes easy to detect design errors and the like during testing, and failures can be detected early.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the invention, Fig. 3 is a schematic diagram of a data processing device, Fig. 4 is a diagram explaining the vector register, and Fig. 5 is a calculation state. The explanatory diagram, FIG. 6, is a conventional example. 1-1 to 1-n-・-Load access pipeline 2-
Vector registers 3-1 to 3-m-Arithmetic pipelines 4-1 to 4-n-Arithmetic pipeline stop request generator 5-Arithmetic pipeline stop signal generator 6-Instruction control unit 12-Clock stop circuit 13-Selection circuit patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Sakae Yamatani Part 1 of Misaki Hara of the Invention Figure 2 An Embodiment of the Invention Figure 2 Illustration of Vector Register Figure 4 Data Illusion Figure 3 Figure 1 Math Diagram 5

Claims (1)

[Claims] At least one or more access pipelines (one
-1 to 1-n), one or more arithmetic pipelines (3-1 to 3-m), a vector processing device having interleaved vector registers (2), and one or more Main storage device and access pipeline (1-1~
a memory access control device for controlling memory access from the main memory device (1-1 to 1-n); By doing so, data is sequentially supplied to the arithmetic pipeline, and the vector register (
2) In a vector processing device that is controlled to stop the clocks of the arithmetic pipelines (3-1 to 3-m) by the number of interleaves in the vector register when the data to be loaded is exhausted, the number of interleaves is forcibly set from the outside. This pipeline control method is equipped with a clock stop means (13) that stops the clock by an integer multiple of , making it possible to detect failures in the control circuit at an early stage when the clock is stopped.