JPS6339036A - Pipeline processing system - Google Patents

Abstract

PURPOSE:To detect the abnormality of a bypass action in a pipeline system by checking the propriety of bypass data. CONSTITUTION:The updating data (a) of an instruction (a) proceeds successively each stage of a pipeline as an operand register 5, a writing register 6 and a buffer register 7 in response to clock cycles t2, t3 and t4. At the same time, the address (aw) of a general-purpose register as well which updates the instruction (a) proceeds to a register 11 and a register 12 together with the updating instruction address (aw) of the general-purpose register of the instruction (a) as well and is transferred to a register 81 and a register 82. In the cycle t3 an instruction (c) is set at a stage A together with an instruction (b) preceding the instruction (c) set at a stage B and the instruction (a) set at a stage C respectively. In such a case, it is checked that the signal BB of a register 88 is set at '1' and that the coincidence is secured between the operand data OD bypassed by the register 5 and the data WD(a') delivered from the register 6. In such a way, the propriety of the bypass data is monitored.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a by-one line processing method.

[Conventional technology]

The conventional pipeline processing method uses a transfer register that transfers address data in full sequential order.

A group of general-purpose registers, an operand register that holds seven operand data, an arithmetic unit that processes all the contents of the operand register, a write-in register that holds all the operation results of the arithmetic unit, and write and read operations to the same general-purpose register. A bypass check circuit that detects all conflicts and normally selects all the contents of the n general-purpose registers specified by the above address data, but when the above conflict is detected, it selects all the outputs of the arithmetic unit or write register and writes them to the operand registers. [Problems solved by the invention and reduced to two] In the above-mentioned conventional method, the data is bypassed in the event of contention, thereby eliminating the need to wait for successive eli operations. The bypass check circuit only detects the establishment of a race condition, and does not check the validity of the bypassed data. The method of the present invention has the drawback that it cannot detect errors and operates using all invalid data. A group of registers, a group of general-purpose registers, and an operand register that holds operand data.

There is an arithmetic unit that processes the contents of the operand register, a bypass check circuit that detects all conflicts between operations, and a bypass check circuit that normally selects the contents of the general-purpose register specified by the above address data, but when the conflict occurs, the operation S The third part is a selection circuit that selects all outputs of the write register and sends them to the operand register.

After data is sent to the operand register during the above conflict, the contents held in the operand register are compared with the contents held in the write register or buffer register, and it is monitored that the contents held in the operand register are valid. Embodiment 1 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a data processing device [1'] according to an embodiment of the present invention.

Referring to FIG. 1, this embodiment includes a transfer register group 1, a general-purpose register group 2, an arithmetic section 31, a selection device 4, an operand register 5, an input register 6, a buffer register 7% bypass check circuit 8, and an instruction control section. 9 Worker's memory 10
In Figure 1, transfer register group 1 consists of
consists of two registers 11 and 12, and the address of a general-purpose register used in an instruction is supplied from the instruction control s9 and transferred sequentially in accordance with the stages of the pipeline.

The general-purpose register group 2 is composed of a plurality of general-purpose registers, and the instruction control unit 9 is given an address of 6%.
1-Register 12 of the last stage of transfer register group 1
This is a group of companion registers that store operands used in calculations, given the address of the FF address.

The calculation unit 3 is a calculation unit that performs calculations on the operands stored in the general-purpose register group 2 and the data in the main memory 10.

The filling register 6 stores the data RD? of the operation result output by the operation s3. This is a register that holds 1- and writes data to the general-purpose register group 2 and main memory 10.

Normally, the selection means 4 selects and outputs all the data output by the general-purpose register group 2, but when the writing operation to the general-purpose register group 2 and the bladder removal operation conflict, the selection means 4 selects and outputs all the data output from the general-purpose register group 2. Either the data RD output by the section 3 or the data WD output by the fill-in register 6 is selected, and the bypass of the F data is performed in order to output that data.

The operand register 5 receives the signal 5D output from the selection means 4.
This is a register that holds t- and supplies operand data to operation s3 and OD'.

Buffer register 7 is a register that holds data WD' output from storage register 6, and is a register used to check the validity of bypass data.

The bypass check circuit 8 controls the selection means 4 to bypass data when a write operation and a read operation to the general-purpose register group 2 conflict, so as not to wait for data. In addition, when bypassing data, it checks whether the bypassed data is valid, detects an abnormality, and outputs a bypass abnormality signal Ask to the outside.

The nine block diagram shown in FIG. 1 is constructed in a pipeline manner and has three stages. The stage 'kA stage where the general-purpose register group 2 and the main memory 10 exist, the stage 'kB stage where the operand register 5 exists, and the stage where the write register 6 exists are called the C stage.

Register 11 in transfer register group 1 is a register on the B stage, and is output by 0 register 12a register 11, which is a register that holds and outputs the address Δ of the n general-purpose register specified by F in the branch instruction output by instruction control s9. This is a register on the C stage that holds the general-purpose register address BNt- and specifies the write address of the general-purpose register group 2.

Let it be the address CN of the general-purpose register held by register 12.

In the bypass check circuit 8, registers 81 and 82 are 1-bit registers that transfer the general register update signal AWk output from the instruction side -s9.
The HB stage register 82 is a register on the C stage, and the general-purpose register update signal tone B held by each
W, CW O general register update signal CW is an update signal to the general register n specified by the general register address CNK held by the register 12.

Comparators 83 and 84 are ninth ones that detect a conflict between a write operation to general-purpose register IR2 and a continuation operation.
4 compares the general-purpose register address AN output by the instruction 1tlJ#m9 with the general-purpose register address BN held by the register 11, and the comparator 83 compares the general-purpose register address AN outputted by the instruction 1tlJ#m9 with the general-purpose register address BN held by the register 11.
General-purpose register address CN held by N and register 12
Compare all.

The comparator 85 compares the operand data OD held by the operand register 5 and the data WD held by the write register 6.
The compensator 86 compares the operand data OD and the buffer data BD held by the buffer register 7.

Registers 87 and 88 are 1-bit registers that hold bypass instructions, and the data W held by the % write register 6.
Dt-The selection signal SO bypassed to the operand register 5 and inputted to the register 87 at 9 o'clock becomes @1'', and the operation s
3 operation result RDt - The selection signal S1 bypassed to the operand register 5 and inputted to the register box at 9 o'clock becomes 11m0 The signal tsonzof' held by the 0 register 87.88
Let them be LCB and BB.

The truth table of the selection means 4 is as follows.0□ The selection signals so and si in this table are given to the selection means 4,
It is expressed by the following logical formula.

SO= (AN=BN)・BW・(AN=CW)・CW
S1= (AN=BW)・BW Here, (AN=BN) is the coincidence signal of the comparator 84, and (A
N=CN) is the match signal of the comparator 83.

The bypass checker circuit 8 checks the validity of the bypass data, detects an abnormal state, and generates a bypass abnormality detection signal AS' at nine times to report it to the outside. Bypass abnormality detection signal ASt1 is expressed by the following logical formula: 0 AS=(OD4WD)・BB+(OD~BD)・CBHere, (OD field WD) is the mismatch signal of the comparator 85, and (O
D#BD) is the discrepancy signal of the comparator 86.

FIG. 2 is a time chart showing the operation of the block diagram explained in FIG. 1.

In FIG. 2, the clock cycle t"jtt*F...
...Jin, and so on. Clock cycle 1. Instruction 8% Instruction b1 Instruction C sequentially advances through each stage of the pipeline.

It is assumed that instruction aid is an instruction that completely updates one general-purpose register, and instruction c is an instruction that is used as an operand for all the contents of the general-purpose register that instruction a updates.

Update data a of instruction a is clock cycle t2°E3p
Corresponding to L4, each stage of the pipeline is sequentially advanced through operand register 5, write register 6, and buffer register 7. At this time, the address aw of the general-purpose register updated by the instruction a is also changed to register 11. The general register update instruction aW of instruction a is also transferred to register 81.
, and the register 82.

At clock cycle t2, when an instruction exists in the A stage, an instruction a preceding the instruction exists in the B stage. When the clock cycle advances from Lm to t3,
The operation result a' of the instruction a is bypassed from the operation unit 3 to the operand register 5.

In clock cycle t3, instruction C exists in A stage, and the instruction preceding instruction C is in B stage, instruction a.
exists on the c stage. At this time, the signal BB of the register 88 is ``1'', and the operand data OD that is bypassed to the operand register 5 and the data WIJ (a') output from the write register 6 (the operation result of instruction a) match. Check that the bypass data is correct and monitor the correctness of the bypass data if the clock cycle is 1. When proceeding from to t4, the operation result a/ of the instruction a is bypassed from the fill-in register 6 to the operand register 5 via the selector 4.

In clock cycle t4, when the instruction C exists in the B stage, the signal CB of the register 87 is "1", and the 2'Lk operand data OD and the buffer data output from the buffer register 7 (of the instruction a) are bypassed to the operand register 5. Calculation result) BD (7) Checks that a matches, and thoroughly monitors the validity of the bypass data.

〔Effect of the invention〕

As explained above, the present invention has the effect that all abnormalities in the bypass operation can be detected by checking the tooth retention property of the bypass data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a time chart explaining the operation of the embodiment shown in FIG.

Claims (1)

[Scope of Claims] A transfer register group that sequentially transfers address data, a general-purpose register group, an operand register that holds operand data, an arithmetic unit that processes the contents of the operand register, and the arithmetic unit A write register that holds the operation result of the write register, a buffer register that holds the output data of the write register, a bypass check circuit that detects a conflict between a write operation and a read operation to the same general-purpose register, and usually a a selection circuit that selects the contents of a designated general-purpose register and, when the conflict is detected, selects the output of the arithmetic unit or the write register and sends it to the operand register; A bypass check circuit is provided which compares the contents held in the operand register with the contents held in the write register or the buffer register after sending, and monitors whether the contents held in the operand register are valid. A pipeline processing method characterized by: