JPS5833580B2 - Diagnostic method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a diagnostic method for a processing device system in which a plurality of processing devices perform asynchronous operations.

In systems equipped with multiple central processing units, key operations from the central testing equipment attached to the system can switch between synchronous mode (system redundant synchronous operation) and separate mode (each operating independently as a separate system). , or multiprocessor mode (each can access the same memory arbitrarily and operate as a single system).

If there is a discrepancy in the operation of two central processing units during redundant synchronous operation, or if a failure occurs in another mode, the work being executed is interrupted, a diagnosis is made, and the affected unit is disconnected. Switch the connection to an alternate device.

Conventionally, in order to diagnose a processing device, as shown in FIG.
This is done by reading a diagnostic program from a common main memory MM, executing it simultaneously, and comparing the results with a matching circuit M.

That is, two central processing units CCO and CC1 share one main memory MM, and both central processing units CCO and CC1 share one main memory MM.
, CC1 is provided, and both devices CCO and CC1 operate in complete synchronization.

In this case, the processing device CCO is assumed to be a diagnostic system, and the processing device CC1 is assumed to be a diagnosed system.

- If the comparison results in the several circuits M are equal, it is determined that it is normal; if not, it is determined that it is abnormal.

At the time of executing the instruction that did not match, the device under diagnosis
1 means that the faulty part was used.

The diagnosis method shown in Fig. 1 can perform diagnosis in a simple manner, but in order to perform synchronous operation by sharing the memo IJMM,
A complicated circuit is required to match the timing, and a matching circuit M is specially required for matching.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional diagnostic methods as described above, and to diagnose a processing device with high accuracy using a simple configuration.

Embodiments of the present invention will be described below with reference to the drawings.

Figure 2 shows the countries that make up the block in this system.

A dedicated main memo IJMM is connected to each of the central processing units CCO and CC1, so that main memos IJMM of other systems cannot be used.

Control between the central processing units CCO and CC1 includes three functions: start and stop of other systems, and register reading functions.

Peripheral devices l10-0 and l10-1 including external memories are connected to the image processing devices CCO and CC1, respectively, but the -number circuit and its equivalent circuit are not connected at all.

However, since the memory refresh circuits for both systems are provided exclusively, the refresh timings are deviated as shown in FIG.

That is, when using a dynamic IC memory, a refresh operation is required, and each memory MMO,
When a refresh clock is sent to MM1 from each processing unit CCO and CC1, memory access is delayed during the memory refresh operation period.
Even if the same program is started at the same time, a difference in instruction execution timing will occur in both systems.

In addition, when the start STA and stop STP are as shown in Fig. 3, there is a difference in the number of refreshes during the program execution period T, and the number of waiting times for access to MMl increases by one, and in CC1 the program progresses accordingly. is delayed.

In addition, there are other problems such as the dedicated use of the main memory and the timing of start and stop of processing, making it extremely difficult to perform diagnosis using the apparatus having the configuration shown in FIG.

Therefore, in the present invention, when the same program is executed in parallel on both systems, when referring to the instruction processing result of the system to be diagnosed, the program in the diagnostic system is replaced with an instruction to stop the system to be diagnosed, and then executed. After the diagnostic system is stopped, by referring to the execution address of the system to be diagnosed, it is determined whether or not the execution command is out of alignment.

A program progress diagram of the diagnostic method according to the present invention is shown in FIG.
Further, examples in which the number of refreshes is the same and the number of refreshes are different are shown in FIGS. 5a and 5b, and a block diagram of the result and address matching circuit at the time of stop is shown in FIGS. 6a and 6b.
Shown below.

First, the main memories MMO and MM of the diagnosis system and the system to be diagnosed
1 stores the same diagnostic program, and the diagnostic system processing unit C
The diagnosis system and the system to be diagnosed are started simultaneously by the finger/+STA from the CO.

As a result, both systems execute the same instruction according to the instruction address shown in FIG.

In this case, once the last instruction has been processed, the results of intermediate processing cannot be referenced.

Therefore, if there is an instruction in the diagnostic system that you want to refer to the execution result of the diagnostic program, the correct data of the execution result is saved in the main memory of the diagnostic system in advance.
In the diagnostic system command, the command whose execution result is to be referred to is replaced in advance with the command 4>STP that stops the system to be diagnosed.

In Figure 4, the life 'eF at address 6 in the diagnostic system is the stop life 4.
>STP, so when the instructions progress simultaneously and reach address 6, the system to be diagnosed executes the instruction +F, while the diagnostic system executes the stop instruction STP.

Then, when the process of life ◆F of the system to be diagnosed is completed, the system to be diagnosed stops.

Next, the diagnostic processing unit CCO sets the correct answer data of life +F prepared in advance in the register RO.

Next, the diagnostic processing unit CCO is the diagnostic processing unit CC1.
Issues a command to read the contents of register RO.

As shown in FIG. 6a, the processing unit CCO of the diagnostic system executes the stop command ◆STP and stops the system to be diagnosed, and then the processing unit CC1 in which the execution result of the command +F is stored.
The register R'0 of is read, and the arithmetic circuit ADD performs an exclusive OR for each pit along with the contents of the register RO in the processing device CCD, which stores the correct data of life 7+F, and as a result, all bits are When it is zero, it is normal, and if even one bit is 1, it is determined that a faulty circuit is used.

In this way, by reading the register R'0 of the system to be diagnosed and comparing it with the correct data, it is possible to determine whether the processing is normal or abnormal.

Note that the sub-diagnosis program for verification performed after stopping the main diagnosis program must be resident in the dedicated memory IJMMO, or at the time of diagnosis, in l10-0 or ■
10-1 from a magnetic tape device or the like.

After referring to the result of command ◆F by the sub-diagnosis program, the original program F is stored again at address 6 in the diagnosis system, and the process ends.

Also, during the memory refresh operation period, the processing of the diagnostic program is stopped as described above, but in this case, both systems use dedicated main memory IJMM and refresh is performed separately, so the refresh timing is A misalignment occurs.

As shown in FIG.
As shown in the figure, when stop order 4>STP, the next order ◆G of the order ◆F that is desired to be stopped is stopped.

Therefore, at the time of stopping, before checking the processing results, the diagnostic system refers to the instruction execution address of the system to be diagnosed to determine whether or not it is the relevant instruction.

That is, as shown in FIG.
After executing , the contents of the location register L of the diagnostic processing unit CC1, which specifies the address of the program instruction to be executed next, are read into the diagnostic processing unit CCO, and the contents of the location register LR of the diagnostic system are calculated together with the contents of the diagnostic processing unit CC1. In circuit ADD, X exclusive for each bit
Take ora.

For example, if the contents of both addresses are 1101, the calculation result will be all zeros, which indicates that the program is the one in question.

If even one bit is 1 in the calculation result, it is not the relevant program, and the process returns to the beginning and starts over with the instruction STA to start the system to be diagnosed.

As described above, according to the present invention, when an instruction is stopped in the middle of a diagnostic program to check the results, it is checked whether the address is the corresponding address or not, so there is no difference in the number of refreshes between the diagnostic system and the system to be diagnosed. Even if there is a difference, there will be no problem if the diagnostic program is repeatedly executed from STA until the difference disappears.

This is because the number of refreshes differs depending on at what point during memory refresh the ST instruction is executed.

In addition, since the processing results are verified and the corresponding address is referenced using a general-purpose arithmetic circuit, there is no need for a matching circuit or other special circuit for verification, and there is no need for a complicated circuit to match the timing. This eliminates the need for processing equipment, making it possible to diagnose the processing device with high precision using a simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional diagnostic method, Fig. 2 is a block diagram of a diagnostic method according to the present invention, Fig. 3 is an explanatory diagram of the difference in the number of memory refreshes, and Fig. 4 is an implementation of the present invention. An explanatory diagram of the progress state of the diagnostic program showing an example. Figures 5a and b are time charts when the refresh counts are the same and when there is a difference. Figures 6a and b are the processing when the program is stopped. FIG. 2 is a block diagram of a result verification circuit and an execution address verification circuit. MM, MMO, MMI: Main memory, M matching circuit, CCO, CC1: Processing unit, l1O-OIlo-1
: Peripheral device, STA Nistart instruction, STP Nistop instruction ◆, RO, R'0: Result accumulation register, LR, LR'
:Location register, ADD: Arithmetic circuit, t:
Refresh period.

Claims (1)

[Claims] 1 In a processing system that connects a semiconductor memory device that requires refreshing and a central processing unit and uses it asynchronously, a diagnostic method in which the same program is executed in parallel on the diagnostic system and the system to be diagnosed and the execution results are collated, In order to refer to the result of processing any command in the system to be diagnosed, replace the same command in the diagnostic system with an instruction to stop the system to be diagnosed, then run both systems at the same time, and after the system to be diagnosed stops, the diagnostic system A diagnostic method characterized in that it is determined whether or not the relevant instruction has stopped by referring to the instruction execution address of the system to be diagnosed, and after the relevant instruction has stopped, the instruction processing result is referred to.