JPH038036B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a refresh synchronization method, and more particularly to a refresh synchronization method that always maintains the same refresh timing of a memory.

In recent years, memory has been widely used in electronic devices.
Some of these memories must be refreshed a required number of times during a predetermined cycle. In other words, the total memory capacity is divided into multiple refresh units, and these divided units are refreshed sequentially, and the refresh time allocated to each divided unit is shared by the multiple divided units. The refresh is executed sequentially within the total time of the program, giving a degree of freedom in giving priority to program execution. In the case of a computer using memory like this one, executing this refresh has a considerable effect on the normal operation of the computer. For example, refresh is unnecessary for operation, and this extra operation can cause logical errors and even prevent the use of the computer. When this logic error occurs, it is common to repeatedly execute the same program on the computer system to investigate the problem. However, the refresh operation is irregular, and there is a problem in that the state in which the fault has occurred is not maintained during the investigation, and the investigation is conducted in the refreshed state at different times, making it difficult to discover the fault.

The present invention was made in view of the above problems, and no matter how many times the same program is executed,
The purpose of the present invention is to provide a refresh synchronization method in which refreshes that affect a program are always performed at the same timing, and in particular, refreshes appear to be performed at the same timing even when artificially operating by one step feed. It is something.

According to the present invention, in a memory refresh synchronization method in which a memory refresh unit is divided into a plurality of units and a required number of refreshes are executed during a predetermined cycle, the first clock counts the cycles. 1 counter, a second counter for counting the number of refreshes, and the first counter;
A first register and a second register are provided for setting respective count values of a second counter with a second clock, and when the second clock is stopped, the first counter is set to the first register value. The refresh is executed until the second register value is reached, and when the first counter is between the first register value and the predetermined cycle, the refresh is executed the remaining required number of times. This is achieved by a refresh synchronization method characterized by the following.

Preferred embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment according to the present invention, where 1 and 2 are first and second counters, 3 and 4 are first and second registers, respectively, 5 and 6 are comparison circuits, and 7 and 2 are first and second counters, respectively, 3 and 4 are first and second registers, respectively, 5 and 6 are comparison circuits, 8 are the first and second clocks, respectively. In the figure, the second counter 2 is a counter that displays the number of refreshes, and the refresh execution signal is inputted, and its output is branched into two branches.One branch passes through the second register 4 and is input to one side of the comparator circuit 6, and the other The branch is directly input to the other side of the comparator circuit 6. On the other hand, the first
Counter 1 is a counter that displays the number of cycles, and a cycle signal is input thereto. The output of this first counter 1 is also branched into two branches; one branch passes through the first register 3 and is input to one side of the comparator circuit 5, and the other branch is directly input to the comparator circuit 5. Note that the first and second counters 1 and 2 and the first and second registers 3 and 4 are reset when the power is turned on. Furthermore, the first and second counters 1 and 2 are operated by a first clock 7 consisting of two consecutive clock trains (hereinafter referred to as free-run clocks), and the first and second registers 3 and 4 are operated by a first clock 7 which can be stopped when required. 2 clocks (hereinafter referred to as gated
It operates at 8 (referred to as a clock). As an example, a description will be given assuming that refresh is executed a required number of times 64 times during a predetermined cycle of 2048 cycles. The maximum count numbers of the first counter 1 and the second counter 2 are 2048 and 64, respectively, and the structure is such that they return to 0 after the maximum count. The first and second registers 3 and 4 store the counts of the first and second counters 1 and 2, respectively, at the gated clock 8, and hold the stored counts while the gated clock 8 is stopped. do the action. The comparison circuit 5 compares the values of the first counter 1 and the first register 3, and if they match, outputs a signal of "0", and also outputs the magnitude of each as a signal. The comparison circuit 6 is the second counter 2
The values of the second register 4 and the second register 4 are compared and their respective magnitudes are outputted as signals. When executing a computer program with the above configuration, when it is first started from the control console, the reset circuit operates and the first and second counters 1 and 2 and the first and second registers 3 and 4 become 0, and the comparator circuit When 5 and 6 match, they both output a signal "0" and the electronic computer starts executing the instruction. That is, the electronic calculation is in a state where the command is executed when the outputs of the comparison circuits 5 and 6 both output the signal "0". This ensures that the clock signal and refresh are synchronized when the program is executed for the first time. If the gated clock is stopped for any reason, both the first register 3 and the second register 4 stop displaying the current cycle number and refresh number. However, counters 1 and 2, which operate with free-run clocks, do not stop and continue to operate. In this state, since the program execution is stopped, only the memory refresh is executed until the required number of times, that is, 64 times.

On the other hand, the cycle signal causes the first counter 1 to
is counted up during that time, and when it reaches a full count, the first and second counters 1 and 2 are simultaneously reset to 0, as will be described later, and the cycle and refresh are started at the same time and synchronized again. The current display values of the first counter 1 and the first register 3 are compared in the comparison circuit 5, and the display values of the second count 2 and the second register 4 are compared in the comparison circuit 6, and both the counter values are the register values. Refresh operation is performed when the value is smaller. In other words, the refresh is executed until the outputs of both comparison circuits 5 and 6 become 0.

At this point, if a signal to increment the gated clock is being output, the outputs of both comparators 5 and 6 will be 0.
The program execution is resumed using
Both the cycle and refresh programs can be restarted from the same conditions as when the gated clock was stopped.

A circuit diagram of an embodiment according to the present invention is shown in FIG.
The same reference numerals are used for the same parts as in Fig. 1. 9 to 1
6 is an AND circuit, 17 to 21 are gate circuits,
22 is a flip-flop circuit. The first counter 1 has a maximum value of 2047, returns to zero when it reaches the maximum value, and has a function of returning the second counter 2 to zero when it reaches this maximum value. The second counter 2 has a maximum value of 63, and the first counter 1
Count the number of times it must be refreshed until it reaches 2047. The first and second registers 3 and 4 are therefore registers that can store 2047 and 68, respectively. First and second registers 3 and 4 and comparison circuit 5
The operations of and 6 have been described above and will therefore be omitted. The second counter 2 has a 7-bit configuration consisting of bits 0 to 6, and the detection signal of the highest bit and the refresh count input of the second counter 2 are input to an AND circuit 9, and its output is sent to a gate circuit 17. The signal is input to the AND circuit 14. The outputs of the gate circuit 11 and the gate circuit 21 are further input to the AND circuit 14. A signal is input to the input of the AND circuit 11 when the difference between the comparison circuits 5 and 6 is small, that is, when the counter is smaller than the register. One gate circuit 21 receives a signal to stop the gated clock. The operations of the AND circuits 9, 11, and 14 and the gate circuit 21 described above are performed until the refresh count input reaches the maximum value of the first counter 2, and when the difference value between the comparison circuits 5 and 6 becomes small, and then the gated clock is When the three conditions for stopping are satisfied, the AND circuit 14 outputs,
The memory continues to be refreshed through the gate circuit 19, and the refresh count is returned to the second counter 2 through the gate circuit 18, and the counter is incremented. When the first and second counters are carried up, when each counter reaches its corresponding register value, the comparison circuits 5 and 6 detect that they are equal, and execute a program run (not shown) as described above. Therefore, synchronization is achieved using the values displayed in the first and second registers. When the gated clock signal is stopped, other competing accesses are not activated. The second operation in normal state is
The refresh count signal, which passes through the AND circuit 10 and further passes through the gate circuit 20 until the register 4 reaches its maximum value, is output to the AND circuit 15 when there is no other access signal and there is no gated clock stop signal from the gate circuit 21. through gate circuits 19 and 1
8 is the same as above, and the output of the AND circuit 14 at this time is prohibited without a gated clock stop signal. Therefore, the first register, the second register 3, 4, which signals the stop of the gated clock, stops counting, and the counters 1 and 2, which are operated by the free-running clock, count the required number of times during each given cycle. Comparing circuits 5 and 6 operate when the above condition, that is, the difference value becomes small, and synchronize when the values of registers 3 and 4 are reached. Next, the case of artificial one-step feeding will be described. When the state that the values of the counter and the register of the comparator circuit 5 are equal and the start pulse signal that starts the electronic computer are input to the S side of the flip-flop circuit 22, and the 1-step sending signal is input to the AND circuit 13, the flip-flop circuit 22 outputs "-1" and is input to the AND circuit 16 together with the clock pulse 7, and the AND circuit 16 outputs one pulse of gated clock. Therefore, the first and second registers each make a step corresponding to one pulse. That is, the second register 3 is located at a position that is advanced by one pulse from the zero point of the comparator circuit 5, and the program is executed from the time that is advanced by one step. Of course, the above explanation was made using one pulse, but the same operation can be performed even if there are many pulses. As a result, this synchronization scheme results in synchronization between the first and second register readings when the gated clock is stopped.

As is clear from the above explanation, the refresh synchronization method according to the present invention is a refresh synchronization method in which refreshes that affect programs are always executed at the same timing, and when this method is applied to a computer system, it can be used for maintenance and fault detection. Above all, it has many advantages.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an embodiment of the refresh synchronization system according to the invention, and FIG. 2 shows a circuit diagram of an embodiment of the invention. In the figure, 1 is the first counter, 2 is the second counter, 3 is the first register, 4 is the second register, 7
is a free running clock and 8 is a gated clock.

Claims (1)

[Claims] 1. In a memory refresh synchronization method in which a memory refresh unit is divided into a plurality of units and refreshes are performed a required number of times during a predetermined cycle, a first counter that counts the cycles using a first clock and the number of times the refresh is performed. a second counter that counts the number of clocks; and a first counter that sets the respective count values of the first and second counters using a second clock.
a register and a second register; when the second clock is stopped, the refresh is executed until the first counter reaches the first register value; 1. A refresh synchronization method characterized in that when one counter is between the first register value and the predetermined cycle, the remaining refreshes are executed the required number of times.