TWI816032B - Multi-core processor circuit - Google Patents

Abstract

A multi-core processor circuit including multiple processor cores, a program memory, a first bus, a data memory and a second bus is provided. The program memory is used to store at least one program instruction. The first bus is coupled between the processor cores and the program memory. The data memory is used to store at least one program data. The second bus is coupled between the multiple processor cores and the data memory. The processor cores are enabled one by one to access the program memory and the data memory, and the remaining of the processor cores are turned off.

Description

multi-core processor circuit

The present invention relates to a processor circuit, and in particular to a multi-core processor circuit.

Due to advances in electronic technology, higher computational complexity can be achieved through the use of multi-core processors. In order to reduce the cost of the chip, a shared memory architecture is often required in multi-core designs. Conventional multi-core memory sharing designs require additional costs in the arbiter, especially program memory and data memory. Therefore, a new architecture is proposed for shared program memory and data memory for multi-core designs, so that by using a time-sharing sharing method, there is no memory arbiter overhead.

The invention provides a multi-core processor circuit that can omit the overhead of a memory arbiter.

The multi-core processor circuit of the present invention includes a plurality of processor cores, a program memory, a first bus, a data memory and a second bus. The program memory is used to store at least one program instruction. The first bus is coupled between the processor cores and the program memory. The data memory is used to store at least one program data. The second bus is coupled between the plurality of processor cores and the data memory. Among them, these processor cores are enabled one by one to access program memory and data memory, and the remaining processor cores are turned off.

Based on the above, in the multi-core processor circuit of the embodiment of the present invention, multiple processor cores will not run at the same time, so access conflicts between these processor cores and program memory or data memory will never occur. Therefore, no additional arbitration program design is required to coordinate program memory and data memory.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a multi-core processor circuit according to an embodiment of the present invention. Please refer to Figure 1. In this embodiment, the multi-core processor circuit 100 includes a plurality of processor cores 110_1~110_n, a program memory 120, a first bus 130, a data memory 140, a second bus 150, a control The circuit 160 and the clock generator 170, wherein the program memory 120 is used to store at least one program instruction INST, and the data memory 140 is used to store at least one program data DATA. Among them, n is a positive integer greater than two.

The first bus 130 is coupled between the processor cores 110_1 ~ 110_n and the program memory 120 , and the second bus 150 is coupled between the processor cores 110_1 ~ 110_n and the data memory 140 . The control circuit 160 is coupled to the processor cores 110_1 ~ 110_n to enable these processor cores 110_1 ~ 110_n one by one, and turn off the remaining processor cores 110_1 ~ 110_n. Then, when one of the processor cores 110_1 ~ 110_n is enabled, the enabled processor cores 110_1 ~ 110_n can operate normally to access the program memory 120 and the data memory 140 . Among them, the enabled processor cores 110_1 ~ 110_n can access the program memory 120 through the first bus 130 and/or access the data memory 140 through the second bus 150 .

Furthermore, the clock generator 170 is used to generate the operating clock CLK to the control circuit 160, and the control circuit 160 only provides the operating clock CLK to the enabled processor cores 110_1~110_n, while the remaining processor cores 110_1~110_n will not receive the operating clock CLK. After the enabling period (ie, the allocated operation period) of the enabled processor cores 110_1 ~ 110_n ends, the control circuit 160 will provide the operating clock CLK to the next enabled processor core 110_1 ~ 110_n.

In the embodiment of the present invention, the control circuit 160 includes a counter 161 and a plurality of temporary registers A~N, where the temporary registers A~N respectively correspond to the processor cores 110_1~110_n, and are used to determine the processor cores 110_1~110_n. Individual enabling periods. In other words, the values stored in the registers A~N determine the individual enabling periods of the processor cores 110_1~110_n. Moreover, the individual enablement periods TA and TB of the processor cores 110_1 ~ 110_n are determined by the properties of each processor core 110_1 ~ 110_n, that is, the processor cores 110_1 ~ 110_n with the same properties can have the same length of enablement period, and Processor cores 110_1~110_n of different natures may have enabling periods of different lengths. In addition, the processor cores 110_1 ~ 110_n with simple processing tasks may have a shorter enablement period, and the processor cores 110_1 ~ 110_n with complex processing tasks may have a longer enablement period. That is, the enabling period of the processor cores 110_1 ~ 110_n may depend on the task complexity and the computing power of each processor core 110_1 ~ 110_n.

The counter 161 is used to count the enabling periods of these processor cores 110_1~110_n. Further, the counter 161 counts according to the operation clock CLK, is reset when the control circuit 160 changes the processor cores 110_1˜110_n to which the operation clock CLK is supplied, and then counts according to the operation clock CLK, and when the counter When the value of 161 reaches the value stored in the corresponding register A~N, the operating clock CLK is provided to the next processor core 110_1~110_n.

FIG. 2 is a timing diagram of a multi-core processor circuit according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2. In this embodiment, two processor cores 110_1 and 110_2 are taken as an example, and the enabling period of the processor core 110_1 is TA (corresponding to the register A), and the processor core 110_2 The enabling period is TB (corresponding to register B). Here, one overall cycle period may be TA+TB. Furthermore, it is assumed that the processor core 110_1 has a simple processing task and therefore has a short enabling period TA, and it is assumed that the processor core 110_2 has a complex processing task and therefore has a long enabling period TB.

At the beginning of the enable period TA, the counter 161 is reset and counting continues. When the value of the counter 161 is equal to the value stored in the register A, it means that the enable period TA reaches the end time point. At this time, the control circuit 160 will provide the operating clock CLK to the processor core 110_2. During the enabling period TA, the processor core 110_1 sequentially executes the operation cycle PM for reading the program memory 120 and the operation cycle DM for reading the data memory 140. The number of the operation cycles PM and DM is for illustration. The embodiment is not limited to this.

Then, when the enable period TB starts, the counter 161 is reset again and continues counting. When the value of the counter 161 is equal to the value stored in the register B, it means that the enabling period TB reaches the end time point. At this time, the control circuit 160 will provide the operating clock CLK to the processor core 110_1 again. During the enabling period TB, the processor core 110_2 will also sequentially execute the operation cycle PM for reading the program memory 120 and the operation cycle DM for reading the data memory 140 .

In an embodiment with two processor cores 110_1 and 110_2, the register A corresponding to the processor core 110_1 can be set to 1200, and the register B corresponding to the processor core 110_2 can be set to 1200, that is, the processor core The ratio of the enabling periods of 110_1 and 110_2 may be 1:1. In another implementation, the register A corresponding to the processor core 110_1 can be set to 2400, and the register B corresponding to the processor core 110_2 can be set to 2400, that is, the ratio of the enabling periods of the processor cores 110_1 and 110_2 is still It can be 1:1. In embodiments of the present invention, depending on the complexity of the task and the computing power of each processor core, even if the ratio of the enabling period of the processor core is the same, it can be set more flexibly.

To sum up, in the multi-core processor circuit according to the embodiment of the present invention, multiple processor cores will not run at the same time, so there will never be a conflict in access between these processor cores and program memory or data memory. Therefore, no additional arbitration program design is required to coordinate program memory and data memory. Another advantage of multi-core processor circuits in time sharing is the flexibility of time sharing by setting the values stored in the register.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100:Multi-core processor circuit 110_1~110_n: Processor core 120:Program memory 130:First bus 140:Data memory 150: Second bus 160:Control circuit 161:Counter 170: Clock generator A~N: temporary register CLK: operating clock DATA: program data INST: program instruction PM, DM: operation cycle TA, TB: enabling period

FIG. 1 is a schematic diagram of a multi-core processor circuit according to an embodiment of the present invention. FIG. 2 is a timing diagram of a multi-core processor circuit according to an embodiment of the present invention.

100:Multi-core processor circuit

110_1~110_n: Processor core

120:Program memory

130:First bus

140:Data memory

150: Second bus

160:Control circuit

161:Counter

170: Clock generator

A~N: temporary register

CLK: operating clock

DATA: program data

INST: program instruction

Claims (10)

A multi-core processor circuit includes: a plurality of processor cores; a program memory used to store at least one program instruction; a first bus coupled between the processor cores and the program memory; a data memory for storing at least one program data; and a second bus coupled between the plurality of processor cores and the data memory, wherein the processor cores respond to receiving an operation one by one The clock is enabled one by one to access the program memory and the data memory, and the remaining processor cores are shut down in response to not receiving the operating clock. The multi-core processor circuit of claim 1 further includes a control circuit coupled to the processor cores to enable the processor cores one by one. The multi-core processor circuit of claim 2 further includes a clock generator for generating the operation clock to the control circuit, wherein the control circuit only provides the operation clock to the enabled processor. core. The multi-core processor circuit as claimed in claim 2, wherein the control circuit has a plurality of registers, the registers respectively correspond to the processor cores, and the individual enabling periods of the processor cores are determined The value stored in the corresponding register. The multi-core processor circuit as claimed in claim 4, wherein the individual enabling periods of the processor cores are determined by the properties of each of the processor cores. The multi-core processor circuit of claim 5, wherein processor cores of the same nature have enabling periods of the same length, and processor cores of different natures have enabling periods of different lengths. The multi-core processor circuit of claim 5, wherein the processor core with simple processing tasks has a shorter enabling period, and the processor core with complex processing tasks has a longer enabling period. The multi-core processor circuit of claim 4, wherein the control circuit includes a counter for counting the enabling periods of the processor cores. The multi-core processor circuit of claim 8, wherein the counter counts according to the operation clock, is reset when the control circuit changes the processor core to which the operation clock is provided, and when the value of the counter When the value stored in the corresponding register is reached, the operating clock is provided to the next processor core. The multi-core processor circuit of claim 1, wherein enabled processor cores access the program memory through the first bus and access the data memory through the second bus.