JPH0436883A - Microprocessor and output port - Google Patents

Abstract

PURPOSE:To output a series of signal patterns of less time base error from an output port by storing time timing data based on an external input signal in a time data register and storing output data in a master latch at the same timing. CONSTITUTION:Data for an arbitrary counted value of FRC is stored in time data registers 1111 to 1114 based on the external signal inputted to an input terminal 40, and arbitrary output data is stored in master latches 1141 to 1144 corresponding to time data registers, thereby outputting a signal having a series of output patterns from a slave latch circuit 1160. Since data is automatically transferred from master latches to the slave latch when output data of an adder 1190 and count data of FRC coincide with each other as the result of comparison, the signal having an arbitrary pattern is sent from the output port to minimize the time base error.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the configuration of a microprocessor and an output port, and provides a microprocessor and an output port with less time base error in signals output via an output port. It is something.

2. Description of the Related Art In recent years, von Neumann microprocessors have been widely used in various fields, and they consist of a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a data storage means for reading and writing digital data. means, an arithmetic means for executing an arithmetic operation on digital data, a data bus connecting an input/output terminal of the data storage means and an input/output terminal of the arithmetic means, based on an instruction sent from the program storage means. a control means for controlling operations of the data storage means and the calculation means; a timing generator for generating an instruction execution timing signal; and selecting a specific instruction stored in the program storage means based on the output of the timing generator. The present invention is characterized in that it is equipped with an instruction selection means. In addition, its typical configuration is
No. 33584 (hereinafter abbreviated as Document 1).

Problems to be Solved by the Invention However, since the Neumann type microprocessor shown in Reference 1 executes data processing in a predetermined order, as the program becomes huge, it is difficult to input data asynchronously. The cycle of acquiring external data and processing the data based on it becomes longer, and as a result, the variation in the time between the occurrence of an event and the output signal sent from the microprocessor, that is, the time base error, becomes considerably large. There is a problem. Conventionally, interrupts have been used to solve problems like this, but even if there is an interrupt request, the microprocessor The problem is that a time base error occurs during the period from when the interrupt is accepted to when the interrupt service routine is actually started.

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art and provides an output port and a microprocessor that can output a series of signal patterns with less time base error.

Means for Solving the Problems To achieve this object, the microprocessor of the present invention includes a free running counter that performs a cyclic counting operation based on a specific clock signal, and a time data that stores at least two types of digital data. storage means; time data selection means for selecting any one of the time data storage means; and count data storage means for storing count data of the free running counter in synchronization with an external input signal. an adder that adds the data of the time data storage means and the data of the time data storage means; a comparison means that compares the count data of the free running counter and the addition data of the adder and outputs a match signal when they match; A pointer that performs a cyclic counting operation based on a coincidence signal output from the comparison means, a master latch section that stores the same number of digital data as the time data storage means, and one of the master latch section is selected. The output port includes a master latch selection means and a slave latch section that takes in the data of the master latch section based on a coincidence signal output from the comparison means.

Further, the output port of the present invention includes a free running counter that performs a cyclic counting operation based on a specific clock signal, an adder that adds count data of the free running counter and time data prepared in advance, and the free running counter that performs a cyclic counting operation based on a specific clock signal. a comparison means that compares the count data of the counter and the output data of the adder and outputs a coincidence signal when they match; a pointer that performs a cyclic counting operation based on the coincidence signal output from the comparison means; a master latch section that stores two or more types of digital data; and a master latch section that stores two or more types of digital data;
The device includes a master latch selection unit that selects one of the master latch units, and a slave latch unit that captures data from the master latch unit based on a coincidence signal output from the comparison unit.

Effect of the Invention With the above-described configuration, the present invention can provide a microprocessor and an output port in which the time base error of the signal outputted through the output port is small.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a microprocessor according to the present invention.

In FIG. 1, TMGRloo is a timing generator that generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and its output signal is transmitted to the PC 200, ICR 900 and FRC.
It is supplied to looo. PLA 300 is a programmable logic array, and stores a program consisting of a group of instructions to be executed sequentially. The PC 200 has a program counter and selects a specific instruction stored in the PLA 300 based on the output signal of TMGRloo.

FRC1000 is a free running counter and T
A cyclic counting operation is performed using the output signals of MGR1 and OO as clock signals. FRCloo data is provided to ICR 900 and output port 1100 via local bus 1400. ICR900 is an input capture register circuit, and external signal input terminal 2
When the edge of the input signal applied to 0 to 27 arrives, the count data of FRClooO at that time is
It is stored in a specific register in the R900 (when the edges of multiple input signals arrive at the same time, the count data of FRCooo is stored in multiple registers), and the input signal bone (not shown) is a flag. It has a function to set. Instructions sent from the PLA 300 are sent to the ALU 400 via the command bus 1300.
, address decoder 600 (indicated as address decoder A in the figure) I address decoder 800 (
In the figure, it is indicated as address decoder B. )＋
Supplied to ICR 900 and output port 1100. Further, the data bus 1200 is connected to the ALU 400. ROM500
．． RAM700. ICR900 and output capo) 11
Connected to 00. ALU 400 is a computing unit that performs arithmetic and logical operations on digital data. R.O.
M500 is a read-only memory that sends pre-stored digital data to data bus 120o. RAM 700 is a random access memory that reads and writes digital data via data bus 1200. The output port 1100 is based on the external signal inputted from the signal input terminal 40, and outputs a series of signal patterns that can be changed according to a program from the signal input terminals 30 to 37. The address decoder 600 selects the address of the ROM 500, and the address decoder 800 selects the address of the RAM 7.
Select address 00.

The operation of the microprocessor of this embodiment configured as described above will be explained below with reference to FIGS. 1 to 3.

The TMGR 100 generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and sends this signal to the PC 200, ICR 900, and FRC.
Supply to looO. The PC 200 selects a specific instruction from the instruction group stored in the PLA 300 based on the Yamao signal of TMGRloo, and the PLA 300 transfers the instruction selected by the PC 200 to the command bus 13.
Send to 00. A, LU 400 executes arithmetic and logical operations on digital data sent via data bus 1200 according to instructions sent from command bus 1300, and sends the results to data bus 12.
Send to 00. Address decoder 600 selects a specific address based on a command sent via command bus 1300, and ROM 500
The digital data stored in the storage means corresponding to the address selected by 00 is sent to the data bus 1200. Address decoder 800 is command bus 130
RAM 700 stores or stores digital data sent from data bus 120o in the storage means corresponding to the address selected by address decoder 800. The already stored digital data is sent to the data bus 1200.

Next, the output port 1100 will be explained using FIGS. 2 and 3. Figure 2 is the output of Figure 1) 1100
FIG. 3 is a configuration diagram showing the internal structure of the system, and FIG. 3 is a timing chart of the main parts.

In FIG. 2, when an external signal is input from the input terminal 40, the FRC register 1180 latches the count data of FRC1 and OOO at that time, and supplies the latched data to the adder 1190. Time data register 1111-1
114 (indicated as time data registers A-D in the figure) is a register that stores timing data for outputting data from the output port, and the time data selection circuit 1120 selects one of the time data registers 1111 to 1114. One register is selected and the digital data stored in the selected register is supplied to adder 1190. Adder 1190 adds the data in FRC register 1180 and the data in the time data register selected by time data selection circuit 1120, and supplies the result to comparison circuit 1130. Comparison circuit 1130 compares the digital data supplied from adder 1190 with the count data supplied from FRClooO in FIG. 1 via local bus 1400, and if they match, sends a match signal to slave latch circuit 1160 and pointer circuit 1
170. Further, the comparison circuit 1130 starts a comparison operation when an external signal is supplied from the input terminal 40, and continues the comparison operation until an overflow signal is supplied from the pointer circuit 1170. Address decoder 1110 (indicated as address decoder C in the figure) follows the command sent from command bus 1300 and sends time data registers 1111 to 1111 through data bus 1200.
An address is selected when storing digital data in 1114. Master latches 1141 to 1144 (indicated as master latches A to D in the figure) are latches that store output data, and the master latch selection circuit 1150 selects one of the master latches 1141 to 1144. The digital data stored in the selected master latch is supplied to the slave latch circuit 1160. Also, address decoder 1
140 (indicated as address decoder D in the figure).

) is connected to the master latch 11 via the data bus 1200 in accordance with the command sent from the command bus 1300.
Addresses are selected when storing digital data in 41 to 1144. The pointer circuit 1170 is the comparison circuit 11
A cyclic counting operation is performed based on the 30 coincidence signals, and count data is supplied to the time data selection circuit 1120 and the master latch selection circuit 1150. Further, the pointer circuit 1170 supplies an overflow signal to the comparison circuit 1130 when the counting operation has completed one cycle. Also,
Pointer circuit 1170 initializes count data in response to an initialization command sent from command bus 1300.

The operation of the output capo-1-1100 configured as described above will be explained.

Arbitrary digital data is loaded into the time data registers 1111 to 1114 by a program. For example, the program may cause the time data register 1111 to
When time data is written to the time data register 1111, the address decoder 1110 first writes the time data register 1111 according to an instruction sent via the command bus 1300.
is selected, and the selected time data register 1111 stores the digital data sent via the data bus 1200. Similarly, time data register 1112
Arbitrary digital data is written in ~1114.

Similarly, arbitrary digital data is written into the master latches 1141 to 1144 by a program.

Time data selection circuit 1120 and master latch selection circuit 1150 select a time data register and a master latch, respectively, according to count data supplied from pointer circuit 1170.

Count data of pointer circuit 1170 is “0”.

For rlJ, r2J, and r3J, the time data selection circuit 1120 selects the time data register 1111゜11.
12, 1113. 1114, and the master latch selection circuit 1150 selects the master latch 1141.114.
2,1143. 1144 respectively.

Next, the operation when outputting a series of output patterns will be explained using FIG. In Figure 3, a is FRCloo
O shows the temporal change in count data in the case of an up counter, 1) shows the external signal input from the input terminal 40, C shows the latch data of the FRC register 1180, and d shows the pointer circuit. 1170, e indicates time data supplied from the time data selection circuit 1120 to the adder 1190, f indicates addition result data supplied from the adder 1190 to the comparison circuit 1130, and g indicates the master latch. Output data supplied from the selection circuit 1150 to the slave latch circuit 1160 is shown, h indicates data output from the slave latch circuit 1160, and i indicates a coincidence signal output from the comparison circuit 1130.

FRClooO is an up counter, and time data registers 1111 to 1114 each contain time data TA.
, TB, TC, and TD are stored, and output data D is stored in master latches 1141 to 1144, respectively.
Assume that A, DB, DC, and DD are stored.

In the initial state, the count data of the pointer circuit 1170 is "0", so the time data selection means 1120 selects the time data register 1111, sends the digital data TA stored in this register to the adder 1190, and outputs the digital data TA stored in this register to the adder 1190. Latch selection circuit 1150 selects master latch 1141 and sends digital data DA stored in this latch to slave latch circuit 1160.

When the leading edge of the external signal input to the input terminal 40 arrives at time t1, the FRC register 118
0 contains the count data N of FRClooO at that point.
1 is latched, and the comparison operation of comparison circuit 1130 is started. The adder 1190 adds the latch data N1 of the FRC register 180 and the time data TA of the time data register 1111, and adds the addition result data N2 (=N
1+TA) is supplied to the comparison circuit 1130. Comparison circuit 1
130 compares the digital data N2 supplied from the adder 1190 with the count data of FRClooO shown in FIG. 1 sent via the local bus 1400, and calculates the count data of FRClooO at time t2 in FIG. becomes equal to N2, the match signal shown in FIG.
170. The slave latch circuit 1160 is the third
As shown in the figure, at the leading edge of the match signal sent from the comparator circuit 1130, the master latch 11
The pointer circuit 1170 latches the digital data DA stored in the pointer circuit 1170 as shown in FIG.
counts up the count data from rOJ to "1" by the coincidence signal. Pointer count data “1”
'', the time data TB is supplied from the time data selection circuit 112o to the adder 1190 as shown in FIG.
output data D from the master latch selection circuit 1150.
B is supplied.

Thereafter, the count data of FRCl and OOO are compared with the data sent by the adder 1190 in the same manner, and at time t3. t4. At t5, the count data of FRcloooo and the addition result data of the adder 119o match, so a match signal is sent out from the comparison circuit 113o. Then, each time a match signal is sent from the comparison circuit 1'' 30, the slave latch circuit 1160 latches the digital data stored in the master latch selected by the master latch selection circuit, and the pointer circuit 117o performs a counting operation.

At time t5, the pointer circuit 117o has a count value of "3".
” becomes rOJ and completes the cycle, so an overflow signal is sent to the comparison circuit 113o.

The comparison circuit 1130 stops the comparison operation in response to this overflow signal, and does not send out a match signal until the leading edge of the external signal input to the input terminal 40 arrives.

When the leading edge of the external signal input to the input terminal 40 arrives at time t6, the FRC register 118
0 is the count data N of FRCloo at that point.
6 is latched, the comparison operation of the comparison circuit 1130 is started, and thereafter the same operation as in the case of times t1 to t5 is repeated.

Therefore, based on the external signal input to the input terminal 40, an arbitrary count number of data of FRCloo is stored in the time data registers 1111 to 1114,
By storing arbitrary output data in master latches 1141 to 1144 corresponding to time data registers 1111 to 1114, a signal having a series of output patterns can be output from slave latch circuit 1160.

In this way, the data transfer from the master latches 1141 to 1144 to the slave latch circuit 1160 is automatically performed by the coincidence detection signal of the comparison circuit 1130 that compares the output data of the adder 1190 and the count data 7 of FRC1OOO. By configuring the time base to output a signal of an arbitrary signal pattern from the output port 1100 after a predetermined time after detecting the leading edge of the external signal input asynchronously from the input terminal 40, There are seven things you can do to minimize errors.

As described above, the microprocessor of the present invention includes a free running counter (FRClooO) that performs a cyclic counting operation based on a specific clock signal, and a time data storage means (time data storage means) that stores at least two types of digital data. registers 1111 to 1114),
Time data selection means (time data selection circuit 1120) that selects any one of the time data storage means, and count data storage means (FRC register 1180) that stores count data of a free running counter in synchronization with an external input signal. and an adder (adder 1190) that adds the data of the count data storage means and the data of the time data storage means, and compares the count data of the free running counter and the addition data of the adder, and if they match, Comparison means for outputting a coincidence signal (comparison circuit 1130)
, a pointer (pointer circuit 1170) that performs a cyclic counting operation based on the coincidence signal output from the comparison means, and a master latch section (master latches 1141 to 11) that stores the same number of digital data as the time data storage means.
44), and master latch selection means (master latch selection circuit 11) for selecting one of the master latch sections.
．． 50) and a slave latch section (slave latch circuit 11130) that captures the data of the master latch section based on the coincidence signal output from the comparing means (output port 1100).

Therefore, the microprocessor shown in FIGS. 1 and 2 can easily output a series of signal patterns with few time base errors.

In the embodiment, the output timing is determined based on the leading edge of the external signal, but the same effect can be obtained by using the trailing edge of the external signal or both edges as a reference.

In addition, in the embodiment, the case where there are four types of output data output from the output port is explained, but the operation is the same in any of the cases 1 to 4. Each latch has a configuration of four trees, but the same effect can be obtained even if two or more latches are provided depending on the complexity of the pattern of the signal output from the output capacitor.

Further, in the embodiment, the free running counter is an up counter, but in the case of a down counter, the same effect can be obtained by adding the data with a negative sign in the FRC register.

Next, FIG. 4 shows a block diagram of the output port of the present invention.

In FIG. 4, an FRC 4000 is a free-running counter that performs a cyclic counting operation using a signal supplied from a terminal 4020 as a clock, and count data of the FRC 4000 is supplied to an adder 4100 and a comparison circuit 4200. Furthermore, adder 4100 is supplied with time data from time data register 4300. and,
When the adder 4100 receives an external signal from the external input terminal 4030, it adds the count data of the FRC 4000 and the time data of the time data register 4300,
The addition result data is supplied to comparison circuit 4200. Comparison circuit 4200 compares the count data of FR,C 4000 and the addition result data of adder 4100, and if they match, supplies a match signal to pointer circuit 4400 and slave latch 4700. Pointer circuit 440o
performs a cyclic counting operation based on the match signal of comparison circuit 4200 and supplies count data to master latch selection circuit 4600. Master latch 4500~453
0 (Master latches A-D& are shown in the figure.

) is a register that stores output data output from the output terminals 4010 to 4o13. The master latch selection circuit 4600 selects one of the master latches 4500 to 4530 based on the count data of the pointer circuit 4400, and supplies the data of the selected master latch to the slave latch. Slave latch 4700 is comparator circuit 4
200, the master latch selection circuit 4
It takes in output data supplied from 600 and outputs it from output terminals 4010 to 4013.

The operation of the output port configured as described above will be explained using the block diagram of FIG. 4 and the timing chart of FIG. 5.

In FIG. 5, a shows the temporal change in count data when the FRC4000 is an up counter, b shows the external signal input from the input terminal 4030, and C shows the signal from the adder 4100 to the comparison circuit 4200. d indicates the output data of the pointer circuit 4400, e indicates the output data supplied from the master latch selection circuit 4600 to the slave latch circuit 4700, and f indicates the output data from the slave latch circuit 4700. data, and g indicates a match signal output from the comparison circuit 4200.

It is assumed that FRC 4000 is an up counter, time data register 4300 stores time data T, and master latches 4500 to 4530 store output data DA, DB, DC, and DD, respectively. In addition, the master latch selection circuit 4600 selects the master latch 4 for the data rOJ, IN'', r2'', r3'' of the pointer circuit 4400.
Select 500, 4510, 4, 520° and 4530, respectively.

In the initial state, the count data of the pointer circuit 4400 is rOJ, so the master latch selection circuit 4600 selects the master latch 4500 and transfers the digital data DA stored in this latch to the slave latch circuit 4.
700.

When the leading edge of the external signal input to the input terminal 4030 arrives at time t1, the adder 4100 adds the count data N of F' RC4, OOO at that time.
1 and the time data T stored in the time data register 4300, and the addition result data is sent to the comparison circuit 4.
Supply 200.

Then, the adder 4100 transfers the addition result data at time t1 to the comparison circuit 4200 until the leading edge of the external signal input to the input terminal 4030 newly arrives.
We will continue to supply.

The comparison circuit 4200 compares the digital data N1+T supplied from the adder 4100 and the count data of the FRC 4000, and at time t2 in FIG.
When the count data becomes equal to N10T, a match signal shown in FIG. 5g is sent to slave latch circuit 4700 and pointer circuits 44, 00.

The slave latch circuit 4700 latches the digital data DA stored in the master latch 4500 at the leading edge of the match signal sent from the comparison circuit 4200, as shown in FIG. 5f, and also latches the digital data DA stored in the master latch 4500, as shown in FIG. The pointer circuit 44.00 counts up the count data from "0" to "1" in response to the coincidence signal.

Thereafter, in the same manner, time t3. t5. For the addition result data from the adder updated at t7, each time t
4. ．． t8. At t8, since the count data of the FRC 4000 match, a match signal is sent from the comparison circuit 4200, as shown in FIG. 5g. Then, each time a match signal is sent from the comparison circuit 4200, the slave latch circuit 4-700 latches the digital data stored in the master latch selected by the master latch selection circuit, and the pointer circuit 4-400 performs a counting operation. conduct.

Therefore, time data is stored in the time data register 4300 in advance, and the master latches 1141 to 114
By storing arbitrary output data in the slave latch circuit 40, a signal that generates a series of output turns is generated based on the external signal input to the input terminal 4030.
It can be output from 00.

As described in ``2'' below, the output port of the present invention includes a free running counter (FRC4000) that performs cyclic counting operation based on a specific zero clock signal, and a function that adds count data of the free running counter and time data prepared in advance. an adder (adder 4100) that compares the count data of the free running counter and the output data of the adder, and a comparison circuit (comparison circuit 4200) that outputs a match signal when they match; A pointer (pointer circuit 4.4.OO) that performs a cyclic counting operation based on the coincidence signal received, a master latch section (master latch 4.500 to 4530) that stores at least two types of digital data, and A master latch selection means (master latch selection circuit 4600) that selects one of the master latch sections depending on the content, and a slave latch section (that takes in the data of the master latch section based on the coincidence signal output from the comparison means). slave latch circuit 4700).

In the embodiment, the number of output terminals of the output port is four, but by increasing/decreasing the data length of the master latch and slave latch, any number of output terminals can be realized in exactly the same way.

Effects of the Invention As described above, the present invention stores time timing data for sending an output signal from an output port in a time data register based on an external input signal, and outputs data at the time timing stored in the time data register. By storing this in the master latch, when the edge of the input signal applied to the external signal input terminal arrives, the signal output timing is added from the count data of the free running counter at that point and the time data of the time data register. , when the output timing of the addition result matches the count data of the free running counter, a signal is automatically output, so a series of signal patterns with less time base error can be output from the output port, and the effect is big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration example of an output port section in the same embodiment, and FIG. 3 is a block diagram of the main parts of FIG. 2. 4 is a block diagram of an output port in an embodiment of the present invention, and FIG. 5 is a timing chart of the main part of FIG. 4. 100...timing generator, 200...
・Program counter, 300...PLA,
4.00...ALU, 500...ROM1
700...RAM1 900...ICR, 100
0,4,000...FRC,1100...Dekapo-
+-11i1i~1114, . 4300...Time data register, 1130.4200...Comparison circuit,
1141-1144,. 4500-4530...
Master latch, 1180, 4700...Slave latch, 1170.4.400...Pointer circuit, 1180...FRC register, 11
90,41.00...adder.

Claims (3)

[Claims] (1) A free running counter that performs a cyclic counting operation based on a specific clock signal, a time data storage means for storing at least two types of digital data, and a time for selecting any one of the time data storage means. a data selection means; a count data storage means for storing the count data of the free running counter in synchronization with an external input signal; an adder for adding the data of the count data storage means and the data of the time data storage means; , a comparison means for comparing the count data of the free running counter and the addition data of the adder and outputting a coincidence signal when they match; and performing a cyclic counting operation based on the coincidence signal output from the comparison means. a pointer; a master latch unit that stores the same number of digital data as the time data storage unit; a master latch selection unit that selects any one of the master latch units; and data in the master latch unit from the comparison unit. A microprocessor equipped with an output port consisting of a slave latch unit that captures based on the output match signal. (2) The microprocessor according to claim 1, wherein the time data selection means and the master latch selection means change selection based on pointer count data. (3) a free-running counter that performs a cyclic counting operation based on a specific clock signal; an adder that adds count data of the free-running counter to time data prepared in advance; and count data of the free-running counter. and the output data of the adder, and outputs a coincidence signal when they match; a pointer that performs a cyclic counting operation based on the coincidence signal output from the comparison means; and at least two types of pointers. a master latch unit that stores digital data; a master latch selection unit that selects one of the master latch units according to the contents of the pointer; and a match between the data of the master latch unit that is output from the comparison unit. An output port with a slave latch section that captures signals based on the signal.