JPH03105487A - Microprocessor - Google Patents

Abstract

PURPOSE:To decrease time-base errors by providing an output port which inputs one master latch part to a slave latch circuit in response to the coincidence signal between one comparison data register and the counted value of a free- running counter. CONSTITUTION:Data on the time difference up to a target point of time when an output signal having a series of signal patterns begins to be sent is sent out of the output port to a data bus 1200 and stored in the comparison data register 1111. Further, time difference data of output signals which are sent out successively corresponding to respective time intervals are stored in registers 1112 - 1114 through a bus 1200. Then data to be outputted at the set time stored in those registers are stored in master latches 1141 - 1144 through the bus 1200. Consequently, the output signal having a series of signal patterns with a small error is obtained from the output port 1100.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to the configuration of a microprocessor, and more particularly to providing a microprocessor with less time base error in signals output through an output port.

2. Description of the Related Art In recent years, von Neumann microprocessors have been widely used in various fields, and they consist of a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a data storage means for reading and writing digital data. a calculation means for executing an operation on digital data; a data path connecting an input/output terminal of the data storage means to an input/output terminal of the calculation means; a control means for controlling the operations of the data storage means and the arithmetic means; a timing generator for generating an instruction execution timing signal; and a timing generator for generating a specific instruction stored in the program storage means based on the output of the timing generator. The method is characterized by comprising a command selection means for selecting the command. In addition, its typical configuration is
No. 33584 (hereinafter abbreviated as Document 1).

Problems to be Solved by the Invention However, since the Neumann type microprocessor shown in Reference 1 executes data processing in a predetermined order, as the program becomes huge, it is difficult to input data asynchronously. The cycle of acquiring external data and processing the data based on it becomes longer, and as a result, the variation in the time between the occurrence of an event and the output signal sent from the microprocessor, that is, the time base error, becomes considerably large. There is a problem. Conventionally, interrupts and other methods have been used to solve problems like this, but even if there is an interrupt request, it is not possible to proceed to interrupt processing until the instruction being executed at that time has been processed. There is a problem in that a time base error occurs during the time period from when the processor accepts an interrupt to when the interrupt service routine actually starts.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a microprocessor having an output port that can output a series of signal patterns with less time base error.

Means for Solving the Problems To achieve this object, the microprocessor of the present invention has a free-running counter that performs a cyclic counting operation based on a specific clock signal, and a comparison data store that stores at least two types of digital data. a storage means, a comparison data selection means for selecting one of the comparison data storage means, and a comparison data selection means for comparing the count data of the free running counter and the data of the comparison data storage means, and outputting a match signal when they match. a means of comparison to
A pointer that performs a cyclic counting operation based on the coincidence signal output from the comparison means, a master latch section that stores the same number of digital data as the comparison data storage means, and one of the master latch section is selected. The device includes a master latch selection means and an output port consisting of a slave latch section that takes in the data of the master latch section based on a coincidence signal output from the comparison means.

Effect of the Invention With the above-described configuration, the present invention can provide a microprocessor in which the time-pace error of the signal outputted through the output port is small.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of the sixth microprocessor of the present invention.

In FIG. 1, TMGR 100 is a timing generator that generates an instruction execution timing signal based on a clock signal supplied to an external clock input terminal 10, and its output signal is transmitted to PC 200, ICR 900 and FRC.
Supplied to IOOO. PLA 300 is a programmable logic array, and stores a program consisting of a group of instructions to be executed sequentially. PC200 is a program counter and selects a specific instruction stored in PLA300 based on the output signal of TMGRIOO.

FRCIOOO is a free running counter and T
A cyclic counting operation is performed using the output signal of the MGR 100 as a clock signal. FRctoo count data is supplied to ICR 900 and output port 1100 via local bus 1400. ICR900 is an input capture register circuit, and external signal input terminals 20~
When an edge of the input signal applied to 27 arrives,
ICR9 count data of FRC1000 at that time
Store it in a specific register in 00 (when edges of multiple input signals arrive at the same time, store F in multiple registers)
RCIOOO count data is stored. ) and has a function of setting an input signal acceptance flag (not shown). Instructions sent from the PLA 300 are sent to the ALU 4 via the control bus 1300.
0 0. Address decoder 600 (indicated as address decoder A in the figure), address decoder 8
00 (Indicated as address decoder B in the figure.

), is supplied to the ICR 900 and the output port 1100. In addition, the data bus 1200 includes ALU400, ROM5
00, RAM700. ICR900 and output port 11
Connected to 00. ALU 400 is a computing unit that performs arithmetic and logical operations on digital data. R.O.
M500 is a read-only memory that sends pre-stored digital data to data bus 1200. RAM 700 is a random access memory that reads and writes digital data via data bus 1200. Output port 1100 outputs a series of signal patterns that can be changed by the program from signal output terminals 30-37.

The address decoder 600 selects the address 7}' of the ROM 500, and the address decoder 800 selects the address of the RAM 700.

The operation of the microprocessor of this embodiment configured as described above will be explained below with reference to FIGS. 1 to 4.

The TMGR100 generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal lO, and sends this signal to the PC200, ICR900 and FRC.
Supply to IOOO. The PC 200 selects a specific instruction from a group of instructions stored in the PLA 300 based on the output signal of the TMGR 100, and the PLA 300 sends the instruction selected by the PC 200 to the command bus 1300. ALU 400 performs arithmetic and logical operations on digital data sent via data path 1200 in accordance with instructions sent from command bus 1300, and sends the results to data bus 1200. Address decoder 600 selects a specific address based on instructions sent via command bus 1300, and
OM 500 sends the digital data stored in the storage means corresponding to the address selected by address decoder 600 to data bus 1200. The address decoder 800 selects a specific address based on a command sent via the command bus 130 (1), and selects a specific address from the RAM 70.
0 stores digital data sent from the data bus 1200 in the storage means corresponding to the address selected by the address decoder 800, or sends already stored digital data to the data bus 1200.

Next, the output port 1100 will be explained using FIGS. 2 to 4. FIG. 2 is a block diagram showing the internal configuration of the output port 1100 shown in FIG. 1, and FIGS. 3 and 4 are timing charts of the main parts.

In FIG. 2, comparison data registers 1111 to 1114 (indicated as comparison data registers A to D in the figure) are registers that store digital data to be compared with the count data of FRCIOOO in FIG. The selection circuit 1120 is a comparison data register 1111.111
One of registers 2, 1113, and 1114 is selected, and the digital data stored in the selected register is supplied to comparison circuit 1180. Comparison circuit 1130
is the FR in FIG. 1 via the digital data supplied from the comparison data selection circuit 1120 and the local bus i4oo.
Compare with the count data supplied from CIOOO,
If there is a match, the match signal is sent to the slave latch circuit 1180.
and is supplied to the ink receiving circuit 1170. Further, the address decoder 1110 (indicated as address decoder C in the figure) inputs digital data to comparison data registers 1111, 1112, 1113, and 1114 via the data path 1200 in accordance with the command sent from the command path 1300. Select an address when storing data.

Master latch 1141, 1142, 1143
．． 1144 (in the figure, master latches A, B,
They are shown as C and D. ) is a latch that stores output data, and the master latch selection circuit 1150 is a latch that stores the output data, and the master latch selection circuit 1150 includes master latch IF41, 1142 . 1143.114
4 is selected, and the digital data stored in the selected master latch is supplied to the slave latch circuit 1160. Further, the address decoder 1140 (indicated as address decoder D in the figure) sends digital data to the master latches 1141, 1142, 1143, and 1144 via the data path 1200 in accordance with the command sent from the command bus 1300. Select the address when storing. The pointer circuit 1170 performs a cyclic counting operation based on the coincidence signal of the comparison circuit 1130, and transfers the count data to the comparison data selection circuit 1120 and the master latch selection circuit 11.
Supply 50.

Furthermore, pointer circuit 1170 initializes count data in response to an initialization command sent from command bus 1300.

Regarding the output boat 1100 configured as above,
The operation will be explained.

Comparison data registers 1111, 1112, 111
3. Any digital data is written into 1114 by the program. For example, when comparison data is written to the comparison data register 1111 by a program, the address decoder 1110 first selects the comparison data register 1111 according to an instruction sent via the command bus 1300, and selects the selected comparison data register 1111. Data register 11l1 stores digital data sent via data bus 1200. Similarly, arbitrary digital data is written into comparison data registers 1112, 1113, and 1114.

In addition, master latches 1141, 1142. 1
Similarly, arbitrary digital data is written to 143 and 1144 by a program.

Comparison data selection circuit 1120 and master latch selection circuit 1150 select comparison data registers 1114 to 1 .
114 and master latches 1141 to 1144, respectively.

Count data of pointer circuit 1170 I O 1'1
1 121131, the comparison data selection circuit 112
0 is comparison data register 1111, 1112, 111
3. Select 1114, master latch selection circuit 115
0 is the master latch 1141, 1142.1143.
1144 respectively.

Next, the operation when outputting a series of output patterns will be explained using FIG.

In FIG. 3, a shows the temporal change in the count data of FRCIOOO, and b shows the pointer circuit 1.
170, C is the comparison data selection circuit 1.
120 indicates comparison data supplied to the comparison circuit 1130, d indicates output data supplied from the master latch selection circuit 1150 to the slave latch circuit 1160,
e indicates data output from the slave latch circuit 1160, and f indicates a coincidence signal output from the comparison circuit 1130.

FRC1000 is a down counter, and comparison data registers 1111, 1112, 1113, and 1114 contain comparison data NA, NB, NC, and ND (
NA>NB>NC>ND) are stored in the master latches 1141, 1142, 1143.
1144 respectively have output data DA, DB,
Assume that DC and DD are stored. In the initial state, the count data of the pointer circuit 1170 is 'O', so the comparison data selection means 1120 selects the comparison data register xtttt and sends the digital data NA stored in this register to the comparison circuit 1130. ,
The master latch selection circuit 1150 is the master latch 11
41 and sends this latch number and the stored digital data DA to the slave latch circuit 1160.

The comparison circuit 1130 receives the digital data NA supplied from the comparison data selection circuit 1120 and the local bus 1.
FRCI shown in Figure 1 sent via 400
The count data of OOO is compared, and when the count data of FRCIOOO becomes equal to NA at time t1 in FIG. 3, a match signal shown in f of FIG.
160 and pointer circuit 1170. The slave latch circuit 1160 latches the digital data DA stored in the master latch 1141 at the rising edge of the match signal sent from the comparison circuit 1130, as shown in FIG. As shown, the pointer circuit 1170 counts up the count data from g 0 1 to 111 based on the coincidence signal. When the count data of the pointer circuit 1170 becomes 11', the comparator circuit 1130 as shown in FIG.
is supplied with comparison data NB from the comparison data selection circuit 1120, and output data DB is supplied from the master latch selection circuit 1150 with the 1 slave latch circuit 1160. After that, the count data of FRCIOOO and the comparison data selection circuit 1120 are supplied in the same manner. A comparison is made with the comparison data selected by , and at times t2, t3. At t4, FR
Since the count data of CIOOO and the comparison data match, a match signal is sent from the comparison circuit 1130. Then, each time a match signal is sent from the comparison circuit 1130, the slave latch circuit 1160 latches the digital data stored in the master latch selected by the master latch selection circuit, and the pointer circuit 1170 performs a counting operation.

Therefore, the data after arbitrary counting is compared with the count data of FRCIOOO at a certain time in the data register 1111. 1112. 1113,111
4 and compare data registers 1111, 1112,
1113. Master latch 11 corresponding to 1114
41. By storing arbitrary data in 1!42, 1143, and 1144, a signal having a series of output patterns can be output from the slave latch path 1160.

Next, the operation when changing the signal pattern output from the slave latch circuit 1160 will be described using FIG. 4.

In FIG. 4, a is the temporal change in count data of FRCIOOO, b is the output data of the pointer circuit 1170, and C is the output data from the comparison data selection circuit 1120 to the comparison circuit 113.
d is the output data supplied from the master latch selection circuit 1150 to the slave latch circuit 1160, e is the output data from the slave latch circuit 1160, and f is the match signal output from the comparison circuit 1130. , g indicate pointer initialization signals supplied via the command bus 1300.

When changing a signal pattern while a certain signal pattern is being output, the pointer circuit 1170 is initialized after rewriting the data in the master latches 1141 to 1144 and the comparison data registers 1111 to 1114. In FIG. 4, the count data of pointer circuit 1170 is 32'.
This shows the operation when the signal pattern is changed when .

At time t3, the data of the master latches 114l to 1144 are set to DA', DB', DC'', DD', and the data of the comparison data registers 1l11 to 1114 are set to NA'.
NB', NO', ND'(NA'>
NB'>NO'>ND"), and the pointer circuit 1170 is rewritten by the pointer circuit initialization signal supplied via the command bus 1300 at time t4.
is initialized. By initializing the pointer circuit 1170, the comparison data is changed to NA', and the data supplied from the master latch selection circuit 1150 to the slave latch is changed to DA', as indicated by NCld. Thereafter, a signal having a new series of output patterns is output from the slave latch circuit 1160 based on the changed comparison data and output data.

By initializing the pointer circuit 1170 when changing the signal pattern in this manner, a new signal pattern can be output in the correct order regardless of the count state of the pointer circuit 1170. Note that the pattern of the output signal can be changed in the same way even when the count state of the pointer circuit 1170 is in any state other than "2'."

In this way, master latches 1141, 1142, 11
43, 1144 to the slave latch circuit 1160 is automatically performed by the match detection signal of the comparison circuit 1130 that compares the count data of the comparison data register ciooo. When a signal with an arbitrary signal pattern is sent out from the output port 1100 after a predetermined time after detecting a signal edge, time base errors can be minimized.

That is, in the embodiment shown in FIG. 1, when an edge of the input signal applied to any of the external signal input terminals 20 to 27 arrives, immediately after that, the ICR 900 transfers the count data of the FRC 1000 to the ICR 900 as timing information at that point. Since the exact arrival time of the input signal can be verified by software, the time difference between the output port 1100 and the target time point at which it starts sending out an output signal with a series of signal patterns Data is sent to the data bus 1200 and stored in the comparison data register 1111, and time difference data corresponding to each time interval of output signals to be sent subsequently is stored in the comparison data registers 1112 to 1114 via the data bus 1200. , the data to be output at each set time stored in the comparison data register is sent to data path 1.
200 to the master latches 1141 to 1144, the output port 1 100 provides an output signal having a series of signal patterns with less time base error.

Therefore, the microprocessor shown in FIGS. 1 and 2 can easily output a series of signal patterns with few time base errors.

In the embodiment, the comparison data register and master latch of the output port each have a configuration of four, but depending on the complexity of the pattern of the signal output from the output port, the number of comparison data registers and master latches may be two or more. Exactly the same effect can be obtained.

Effects of the Invention As described above, the present invention provides a free running counter (F) that performs a cyclic counting operation based on a specific clock signal.
RCIOOO), comparison data storage means (comparison data registers 1111 to 1114) that stores at least two or more types of digital data, and comparison data selection means (comparison data selection circuit) that selects any one of the comparison data storage means. 1120), comparison means (comparison circuit 1130) that compares the count data of the free running counter and the data of the comparison data storage means and outputs a coincidence signal if they match, and a coincidence signal output from the comparison means. a pointer (pointer circuit 1170) that performs a cyclic counting operation based on the comparison data storage means, a master latch section (master latches 1141 to 1144) that stores the same number of digital data as the comparison data storage means, and any one of the master latch sections. an output port (output port) consisting of a master latch selection means (master latch selection circuit 1150) that selects the master latch, and a slave latch section (slave latch circuit 1180) that takes in the data of the master latch section based on the coincidence signal output from the comparison means. By providing the port 1100), it is possible to obtain a microprocessor that can output a series of signal patterns with few time base errors, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a microprocessor in an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the configuration of the output port section, and FIGS.
2 is a timing chart of the main parts of the figure. 100...timing generator, 200...
・Program counter, 300...PLA,
400...ALU1 500...ROM,
700...RAM1 900...ICR1 1
000...FRC11 100...Output boat,
1111-1114... Comparison data register,
1130...Comparison circuit, 1141-1144...Master latch 11160...Slave latch, 1
1 7 0 ゜゜゜Pointer circuit.

Claims (3)

[Claims] (1) A free-running counter that performs a cyclic counting operation based on a specific clock signal, a comparison data storage means that stores at least two types of digital data, and a comparison that selects any one of the comparison data storage means. data selection means; comparison means for comparing the count data of the free running counter and the data of the comparison data storage means and outputting a coincidence signal when they match; a pointer that performs a cyclic counting operation; a master latch unit that stores the same number of digital data as the comparison data storage unit; a master latch selection unit that selects any one of the master latch units; and data of the master latch unit. and an output port consisting of a slave latch unit that takes in the matching signal based on the coincidence signal output from the comparing means. (2) The microprocessor according to claim 1, wherein the comparison data selection means and the master latch selection means change selection based on pointer count data. (3) The microprocessor according to claim 1, wherein the pointer is set to an initial counting state by an instruction of the microprocessor.